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Visitor manojhan
Visitor
6,033 Views
Registered: ‎02-15-2016

Timing Analysis - Xilinx ISE 14.7/Spartan 6 FPGA

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Hello,

We are working on a project which involves sampling ADC data, and sending out the sampled data as UDP packets using Spartan 6 FPGA. We used TEMAC core, and an external PHY, the design is FPGA proven. 

 

We haven't done any timing analysis for the design yet, and wanted to do the same. But are clueless, on what has to be done, and how to go about it. Any suggestions on where to start would be a great help for us. We using Xilinx ISE-14.7.

 

Thanks,

Manoj

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Xilinx Employee
Xilinx Employee
11,387 Views
Registered: ‎08-01-2008

Re: Timing Analysis - Xilinx ISE 14.7/Spartan 6 FPGA

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1. use constraint in your design
http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf

add constraints in your project ucf file

2. run implementation and check timing report. your dsign should meet timing
Thanks and Regards
Balkrishan
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Historian
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6,014 Views
Registered: ‎01-23-2009

Re: Timing Analysis - Xilinx ISE 14.7/Spartan 6 FPGA

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Unfortunately, this is not something that can be "taught" on Forum posts. The concepts of static timing analysis and constraints are complex...

 

If you are serious about learning this, Xilinx offers classes through their network of Authorized Training Providers (ATPs). However, you would need to find an ISE based classes. The complete set of classes for ISE are these:

 

Essentials of FPGA Design

Designing for Performance

Advanced FPGA Implementation

 

Static timing analysis and constraints are scattered throughout the three classes, intermixed with tool flow, device architecture, and more advanced concepts...

 

Avrum

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Xilinx Employee
Xilinx Employee
11,388 Views
Registered: ‎08-01-2008

Re: Timing Analysis - Xilinx ISE 14.7/Spartan 6 FPGA

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1. use constraint in your design
http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf

add constraints in your project ucf file

2. run implementation and check timing report. your dsign should meet timing
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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Explorer
Explorer
6,005 Views
Registered: ‎11-25-2015

Re: Timing Analysis - Xilinx ISE 14.7/Spartan 6 FPGA

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@manojhan

 

You can use ISE constraints editor and the constraints will be saved in a ucf file. Refer http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/pce_c_overview.htm for more details

 

Thanks,

Sravanthi

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Visitor manojhan
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5,965 Views
Registered: ‎02-15-2016

Re: Timing Analysis - Xilinx ISE 14.7/Spartan 6 FPGA

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Thank you everyone for your inputs. Will get in touch soon with more specific questions:)

 

Regards,

Manoj

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