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Explorer
Explorer
175 Views
Registered: ‎09-08-2009

Timing Analysis input clock default Jitter value

 

What is the default jitter and skew value used by timing analysis

  • I want to know if my input clock to the FPGA is OK.
  • I using input clock directly (Input Clock from MicroController > MRCC > BUFG > global clock tree

 

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Xilinx Employee
Xilinx Employee
126 Views
Registered: ‎07-16-2008

回复: Timing Analysis input clock default Jitter value

The text and GUI of the Report Timing command expose the breakdown of the clock uncertainty for each timing path.

e.g.

clock_unc.JPG

By default, Total System Jitter (TSJ) is set to 0.071 ns. If the clock is derived from MMCM/PLL, the Discrete Jitter and Phase Error will be calculated and accounted for automatically by tool based on the specified input clock jitter.

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