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Registered: ‎11-29-2015

Timing Closure - Looking for more detail on how to avoid having too many levels of logic

I have timing issues that are caused by super high fanout and I'm looking for more detail on some of the suggestions listed in https://www.xilinx.com/support/answers/9417.html

  1. Issue State Machine Optimization Suggestions 
  2. Use CASE statements instead of nested IF-ELSE statements. 
  3. Use 3-state instead of large muxes (7 or more inputs). What would be a VHDL code example of this?
  4. Use creative math; shift instead of multiplying by multiples of two. Doesn't Vivado already convert multiply and divide operations that are multiples of 2 to left and right shift operations? Do I really need to explicitly specify this?
  5. Use decoders instead of comparators. 
  6. Balance logic around registers.
  7. Pyramid logic with parentheses instead of serial implementation. What would be a VHDL code example of this?
  8. Use IF-THEN-ELSE statements only to do the following:
    • Pre-decode and register counter values.
    • Add a level of pipelining to pre-decode and register input signals.
  9. Use muxes with more than 7-bit wide buses only to do the following:
    • Instead of logic, use registers that are in a 3-state condition. What would be a VHDL code example of this?
    • Drive enable signals from registers; 3-states are in a 3-state condition when enable signals are "1," and drive signals when the enable is "0". What would be a VHDL code example of this?
    • Use floorplan 3-states. ??
  10. Add pipeline registers.



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2 Replies
Scholar markcurry
Registered: ‎09-16-2009

Re: Timing Closure - Looking for more detail on how to avoid having too many levels of logic

Edit to add: 

Forgot the most basic note - read the UltraFast Design Methodology guide stuck at the top of this forum!


End edit...

First of all, are you certain that your timing problems are caused by "super high fanout" nets?

The document listed below, while having good general advise, was written 6 years ago and (originally) targeting ISE 10.1.  Things have changed quite a bit in the years since.

High fanout nets are quite efficiently handled in Vivado - by the later stages of the implementation flow - i.e. after synthesis.  In fact synthesis (or manually user inserted) fixes addressing high fanout usually work against the efficient solutions done by Vivado in the latter stages.  In the 2018 releases the tool actually does some optimizations towards removing synthesis added (or user added) fanout fixes.

I've never had an instances yet where I've needed to manually take some sort of action regarding high-fanout nets.  I just let Vivado do it's job.  (There are other's that prefer more hand-tuned solutions - and that's ok - but really should be reserved for the advanced use cases).

Back to the original problem - reducing levels of logic is a good tool towards addressing timing problems.  I've found that once you've learned the coding techniques, one generally establishes those design patterns quickly.  i.e. the experienced designer doesn't fall into these coding problems very often.  The tools are quite good at inferring and optimizing a lot. 

The (unfortunate) corollary to this is you're not going to get much better performance by tweaking your coding style or playing with the tools settings.  Architecture level changes (as in adding pipelining) are usually what's required.



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Registered: ‎06-21-2017

Re: Timing Closure - Looking for more detail on how to avoid having too many levels of logic

Regarding item 3 and any other references to three state code, there are no tri-statable drivers in a modern FPGA except on the IO.  You can write three state code, but the synthesis tool will just create a mux.  That's certainly true of ISE and Synopsis.  I expect it's true of Vivado, but I haven't tried it. 

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