01-17-2019 04:12 PM
I have timing issues that are caused by super high fanout and I'm looking for more detail on some of the suggestions listed in https://www.xilinx.com/support/answers/9417.html
01-17-2019 04:39 PM - edited 01-17-2019 04:43 PM
Edit to add:
Forgot the most basic note - read the UltraFast Design Methodology guide stuck at the top of this forum!
First of all, are you certain that your timing problems are caused by "super high fanout" nets?
The document listed below, while having good general advise, was written 6 years ago and (originally) targeting ISE 10.1. Things have changed quite a bit in the years since.
High fanout nets are quite efficiently handled in Vivado - by the later stages of the implementation flow - i.e. after synthesis. In fact synthesis (or manually user inserted) fixes addressing high fanout usually work against the efficient solutions done by Vivado in the latter stages. In the 2018 releases the tool actually does some optimizations towards removing synthesis added (or user added) fanout fixes.
I've never had an instances yet where I've needed to manually take some sort of action regarding high-fanout nets. I just let Vivado do it's job. (There are other's that prefer more hand-tuned solutions - and that's ok - but really should be reserved for the advanced use cases).
Back to the original problem - reducing levels of logic is a good tool towards addressing timing problems. I've found that once you've learned the coding techniques, one generally establishes those design patterns quickly. i.e. the experienced designer doesn't fall into these coding problems very often. The tools are quite good at inferring and optimizing a lot.
The (unfortunate) corollary to this is you're not going to get much better performance by tweaking your coding style or playing with the tools settings. Architecture level changes (as in adding pipelining) are usually what's required.
01-17-2019 05:07 PM
Regarding item 3 and any other references to three state code, there are no tri-statable drivers in a modern FPGA except on the IO. You can write three state code, but the synthesis tool will just create a mux. That's certainly true of ISE and Synopsis. I expect it's true of Vivado, but I haven't tried it.