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alexgiul
Explorer
Explorer
6,261 Views
Registered: ‎02-18-2008

Timing Constraint

Hi,

 

I implement my design and with post-route simulation, I notice the signals are delayed:

for example I put the value x"5" on the bus, but in the simulation I see for a short time x"4" and after x"5"....

 

How can I solve it? is it normal?

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bassman59
Historian
Historian
6,247 Views
Registered: ‎02-25-2008


alexgiul wrote:

Hi,

 

I implement my design and with post-route simulation, I notice the signals are delayed:

for example I put the value x"5" on the bus, but in the simulation I see for a short time x"4" and after x"5"....

 

How can I solve it? is it normal?


Wow, could you give us even less information?

----------------------------Yes, I do this for a living.
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ywu
Xilinx Employee
Xilinx Employee
6,240 Views
Registered: ‎11-28-2007

 That is normal because the post-route simulation also includes delay data. Different bits in a bus will have different routing delay, that's why you will see an uncertainty window.

 


alexgiul wrote:

Hi,

 

I implement my design and with post-route simulation, I notice the signals are delayed:

for example I put the value x"5" on the bus, but in the simulation I see for a short time x"4" and after x"5"....

 

How can I solve it? is it normal?


 

 

Cheers,
Jim
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alexgiul
Explorer
Explorer
6,238 Views
Registered: ‎02-18-2008

Hi bassma59,jimvu

 

you're right I forgot the design at home :).... Tomorrow I'll put the design...

 

I put the last timing simulation, the first "strange" transition is on value x"0" to x"5" but there are a lot...

 

  

 I try to explain the design: I have the Spartan3e starter kit and I'm sending an UDP packet.

The incoming clock is used to clocked the output signals (TX_DATA & TX_EN)

 

I have made 2 design, one the older works perfectly instead of this (you see the waveform and I check s the same as older) that never works.

 

Te first difference is on delay : for example in older design, the data on TX_DATA is placed after a small amount of time after the falling edge, instead of this new design, in which the data (the first bytes- after the delays increase) is place around the middle...

 

In the older design I haven't seen strange transitions or similar delays on single bit of the bus (ex TX_DATA)....

 

My question is: I try to create a group constraint on TX_DATA lines, and I put a OFFSET constraint to this group, I think ths constraint should affect the post-map & route simulation, instead I haven't notice anything,

what I would is place the start of "TX_DATA" he closest possible to falling edge, how can I do this???

 

I hope this infos help you

 

Thanks a lot for your support 

 

 

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alexgiul
Explorer
Explorer
6,216 Views
Registered: ‎02-18-2008

I put the code...

 

into the folder "do" you will find the "do" file for simulation of post-place & map design

 

thanks a lot

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