Timing Constraints Wizard Input delay parameters

[davidfhorowitz@lmco.com]

Hello, 

I am working on applying timing constraints using the Timing Constraints Wizard. In my system, I have an ADC that feeds data to the FPGA. The ADC provides a "data ready" signal which the FPGA uses to clock in the data. From my understanding, I need to specify "source" in the Synchronous column of the wizard for these signals. The wizard provides two fields to fill in, "dv_bre" and "dv_are". How would I calculate these values? I have the trace delay values calculated from the PCB and the timing specifications of the ADC from its datasheet. 

The way I understand it, my calculations are as follows:

dv_bre = amount of time data is valid before data ready - trace delay delta from data ready

dv_are = amount of time data is valid after data ready - trace delay delta from data ready 

Does this make sense or I am I making a mistake? 

Thank you. 

[markg@prosensing.com]

Hi David,

Please provide a link to the datasheet for your ADC - and tell us which timing diagram in the datasheet describes how you want to communicate with the ADC.

Also, tell us how fast (Msps) you will be running the ADC.

Using the Timing Constraints Wizard is one way to write constraints for the ADC-to-FPGA interface.  However, you can also type the constraints yourself into the Vivado .xdc file.  Please take a look at the following post for an example of the constraints and architecture used to receive data from an ADC via a Source Synchronous DDR interface.

https://forums.xilinx.com/t5/FPGA-Configuration/ADC-LVDS-data-capture/m-p/1180927#M20504

Cheers,
Mark

[davidfhorowitz@lmco.com]

Thank you for your response.

https://www.ti.com/lit/gpn/ads5444-ep 

We are running the ADC at 200 MHz which is being provided to the ADC from an external clock generator IC.

[markg@prosensing.com · Accepted solution]

The interface between your ADS5444 13-bit ADC and the FPGA is called Source-Synchronous Single Data Rate (SDR).  The interface consists of:

• one LVDS data-clock called DRY in the ADS5444 datasheet.  Let's say that this clock enters your FPGA on the clock-capable LVDS pin-pair called (DCLK_P, DCLK_N)
• thirteen LVDS data lines called D[12:0] in the datasheet.  Let's say that they enter the FPGA on LVDS pin-pairs called (SDAT_P[n], SDAT_N[n]), n=12 downto 0

For a 200MHz data clock, a general form of the constraints for this interface is:

create_clock -period 5.000 [get_ports DCLK_P]​
set_input_delay -clock [get_clocks DCLK_P] -max td_max [get_ports {SDAT_P[*]}]
set_input_delay -clock [get_clocks DCLK_P] -min td_min [get_ports {SDAT_P[*]}]

...where I have used the wildcard (*) to make the set_input_delay constraints apply to all thirteen LVDS data lines.  In the set_input_delay constraints, td_max and td_min can be written as follows:

td_max = tper - dv_bre + ddt_max
td_min = dv_are + ddt_min

where (in nanoseconds):

• tper = period, 5.00, of the 200MHz data clock
• ddt_max = maximum delay difference (data_trace_delay minus clock_trace_delay)
• ddt_min = minimum delay difference (data_trace_delay minus clock_trace_delay)
• dv_bre = tsu_DR from the ADS5444 datasheet
• dv_are = th_DR from the ADS5444 datasheet

If the board traces that bring the data-clock from the ADC to the FPGA are roughly the same length as the board traces that bring the data lines from the ADC to the FPGA then you can accurately use ddt_max=ddt_min=0.

[davidfhorowitz@lmco.com]

Thank you for your help. I greatly appreciate it!

[davidfhorowitz@lmco.com]

One other question:

What would the effect be if to what you explained if the data clock (DRY) from the ADC is routed to non-clock capable pins?

Thank you

[markg@prosensing.com]

What would the effect be if to what you explained if the data clock (DRY) from the ADC is routed to non-clock capable pins?

The effects range from "bad" to "very bad" depending on the architecture you use in the FPGA to capture the data coming from the ADC.  The "bad" being harder to pass timing analysis and the "very bad" being that the architecture can't be used because it requires the clock to come from a clock-capable pin.

This would be a good topic for another post, "Source Synchronous SDR Input without Clock-Capable Pin".  If you start this other post, please again give ADC part#, FPGA part#, and interface clock speed (MHz).

[davidfhorowitz@lmco.com]

Good to know. Thank you for the information. You've been extremely helpful.

[markg@prosensing.com]

I am just reading Avrum's response to your other post, and he reminds me that one more constraint is needed for your source-synchronous SDR input interface.  In particular, you need to specify the jitter of the interface clock using a constraint similar to the following:

set_input_jitter [get_clocks -of_objects [get_ports DCLK_P]] X.XX

 
In this constraint, X.XX, is the jitter.  Xilinx documentation is not clear on the units for jitter, although it seems to be Peak-to-Peak jitter in nanoseconds, which is approximately 14 times the RMS jitter in nanoseconds.

Finally, sometimes we send the interface clock to an MMCM and then use the clock output of the MMCM to capture the data from the interface.  If you are doing this, then it is the MMCM itself that mostly determines the jitter of the capture clock - and the value that we specify using the set_input_jitter constraint typically has only a small effect.