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Visitor yogi_raj_143
Visitor
9,860 Views
Registered: ‎09-29-2008

Timing/Constraints across DCM generated clocks

Hello All, 

 

In my desing I have a top clock 'clk' with period 10ns. The top clock 'clk' is driving a DCM that generates clk_2x that has double the freq, period=5ns

The DCM generated internal clock is driving some flops & outputs from these flops pass through some combinational before going to output pad. 

I want to constraint such output port with output_delay of 1, ie, only 4 seconds are available for (clk_2x)Reg to Output 

 

As per UCF guidelines, I can constraints only with respect to top level clock,  So how should I constraint such 'clk_2x' reg to output ports

 

If i try to constraint with respect to top clock 'clk', how should I do that

 

1. OFFSET = OUT 4 AFTER clk 

Or 

2. OFFSET = OUT 9 AFTER clk 

Or

3.  

OFFSET = OUT 4 AFTER clk RISING

OFFSET = OUT 4 AFTER clk FALLING

 

Not sure if Timing analyzer can take care that output is driven by 2x clock 'clk_2x' so accordingly adjust the OFFSET constraints.

 

When search for this such path in 'twr' timing report, the path contains an delay name 'Tdmcko_CLKFX' which has some odd value "-5.656"

So what is this 'Tdmcko_CLKFX'. Does it hase anything to do with OFFSET adjustment for 2x clock 'clk_2x'

 

-> Well there is related thread in this forum and suggestion was to use IOB, but thats not feasible in my case

 

--

YogS 

 

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3 Replies
Xilinx Employee
Xilinx Employee
9,807 Views
Registered: ‎07-30-2007

Re: Timing/Constraints across DCM generated clocks

OFFSETs allow more detailed specification of paths by either the IOB instances and/or the flop register. One or a combination of both should allow you to more specifically specify which exception paths you want.  See the Xilinx Constraints Guide:

 

Group OFFSET OUT Example

TIMEGRP “pad_group” OFFSET = OUT time units AFTER “clock_pad_net”
TIMEGRP “register_group”;

where

• pad_group is the user- created group of output pads
• time is the time allowed for the data to propagate from the pad to meet a setup
requirement to the clock. This value is in relationship to the clocks initial edge at the
pin of the chip. (The PERIOD constraint defines the clock initial edge.)
• units is ms, micro, ns (default) or ps
• clock_pad_net is the name of the clock using the net name attached to the pad
• register_group is the user-created group of synchronous elements

 

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Xilinx Employee
Xilinx Employee
9,795 Views
Registered: ‎08-10-2008

Re: Timing/Constraints across DCM generated clocks

The reference clock pin in the OFFSET OUT line could ONLY be a pad name.

From the timing report, you could know the clock path delay from the clock pad to the regiter clk2x pin. So you could adjust the delay value in your constraint line, according to this clock path delay.

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Visitor autohzhz
Visitor
9,529 Views
Registered: ‎05-11-2008

Re: Timing/Constraints across DCM generated clocks

I have a similiar question about Tdmcko_clk:
The instantiation port map of a DCM to provide 0 phase-shift between the
external LCLK_IN and the internal CLK is shown below.
 
---------------------
   port map (
      CLK0 => CLK,           -- 0 degree DCM CLK ouptput
      CLK180 => open,       -- 180 degree DCM CLK output
      CLK270 => open,       -- 270 degree DCM CLK output
      CLK2X => open,        -- 2X DCM CLK output
      CLK2X180 => open,  -- 2X, 180 degree DCM CLK out
      CLK90 => open,         -- 90 degree DCM CLK output
      CLKDV => open,        -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => open,         -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,   -- 180 degree CLK synthesis out
      LOCKED => open,      -- DCM LOCK status output
      CLKFB => CLK,         -- DCM clock feedback
      CLKIN => LCLK_IN, -- Clock input (from IBUFG, BUFG or DCM)
      RST => RESET            -- DCM asynchronous reset input
   );
---------------------
 
 
The timing constraint is shown below; I believe that the OFFSET constraints
should be effective since the phase-shift, 0 in this case, due to the DCM on
LCLK_IN, is accounted for by the PAR tool.
---------------------
 NET "LCLK_IN" TNM_NET = LCLK_IN;
 TIMESPEC TS_LCLK_IN = PERIOD "LCLK_IN" 10 ns HIGH 50%;
 OFFSET = IN 8 ns BEFORE "LCLK_IN";
 OFFSET = OUT 7 ns AFTER "LCLK_IN";
---------------------
 
 
A portion of the timing report (.twr) is shown below:
Note the Clock Path Delay of 4.979ns which the DCM usage has failed to
eliminate in this attempt. I was expecting that the delay would be 0ns or
very close to 0ns.
 
---------------------
Slack:                  -5.472ns (requirement - (clock arrival + clock path
+ data path + uncertainty))
  Source:               READY_CARRIER (FF)
  Destination:          LAD<30> (PAD)
  Source Clock:         CLK rising at 0.000ns
  Requirement:          7.000ns
  Data Path Delay:      7.313ns (Levels of Logic = 3)
  Clock Path Delay:     4.979ns (Levels of Logic = 3)
  Clock Uncertainty:    0.180ns
  :
  :
  Maximum Clock Path: LCLK_IN to READY_CARRIER
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D14.I                Tiopi                 0.963   LCLK_IN
                                                       LCLK_IN
                                                       LCLK_IN_IBUFG
    DCM_ADV_X0Y3.CLKIN   net (fanout=1)        1.260   LCLK_IN_IBUFG
    DCM_ADV_X0Y3.CLK0    Tdmcko_CLK           -2.213   DCM_BASE_inst
                                                       DCM_BASE_inst
    BUFGCTRL_X0Y23.I0    net (fanout=3)        1.504   CLK1
    BUFGCTRL_X0Y23.O     Tbgcko_O              0.900   CLK_BUFG
                                                       CLK_BUFG
    SLICE_X52Y103.CLK    net (fanout=123)      2.565   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.979ns (-0.350ns logic,
5.329ns route)
---------------------
 
 
Can anyone shed light on this problem?
 In my opion, Tdmcko_CLK +net CLK1+ Tbgcko_O + net CLK =-2.213+1.504+0.9+2.565

 should equal to the integer times of the period of LCLK_IN, however, the fact is not.

I want to remove the buffer delay, So I have routed the output of the BUFG
back to the CLKFB input of the DCM.

Why? How do you solve this problem?

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