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jihokim
Visitor
Visitor
266 Views
Registered: ‎02-06-2020

Timing Error - Setup Slack

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In Timing, Worst Negative Slack and Total Negative Slack of Setup are displayed in red as shown below.

What is the cause of this?

How can I solve this problem?

In Timimg, Hold and Pulse Width are normal.

jihokim_0-1616660221103.png

 

 

And there are 19 critical warnings in the implementation.

What is the cause of this?

 

The contents of 19 critical warnings are as follows.

 

  • Synthesis
  • synth_1
  • [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group clk_125mhz_mux_x0y0'. ["D:/Zynq/AX7015_EN/course_s1/course_s1/13_PCIe_test_x1/PCIe_test.srcs/constrs_1/new/pcie.xdc":74]
  • Implementation
  • Design Initialization
  • [Common 17-55] 'set_property' expects at least one object. ["D:/Zynq/AX7015_EN/course_s1/course_s1/13_PCIe_test_x1/PCIe_test.srcs/constrs_1/new/pcie.xdc":16]
  • Opt Design
  • [Timing 38-250] Generated clock clk_250mhz_mux_x0y0 has only disabled paths from master clock clk_250mhz_x0y0. Resolution: Analyze why a timing arc is disabled between the master clock and the generated clock. If this expected, remove the definition of the generated clock because it is not needed by your design. If this is not expected, modify the design or the constraint that is causing the problem.
  • Place Design
  • [Timing 38-250] Generated clock clk_250mhz_mux_x0y0 has only disabled paths from master clock clk_250mhz_x0y0. Resolution: Analyze why a timing arc is disabled between the master clock and the generated clock. If this expected, remove the definition of the generated clock because it is not needed by your design. If this is not expected, modify the design or the constraint that is causing the problem.
  • Route Design
  • [Timing 38-250] Generated clock clk_250mhz_mux_x0y0 has only disabled paths from master clock clk_250mhz_x0y0. Resolution: Analyze why a timing arc is disabled between the master clock and the generated clock. If this expected, remove the definition of the generated clock because it is not needed by your design. If this is not expected, modify the design or the constraint that is causing the problem.
  • [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
  • Write Bitstream
  • [Timing 38-250] Generated clock clk_250mhz_mux_x0y0 has only disabled paths from master clock clk_250mhz_x0y0. Resolution: Analyze why a timing arc is disabled between the master clock and the generated clock. If this expected, remove the definition of the generated clock because it is not needed by your design. If this is not expected, modify the design or the constraint that is causing the problem.

 

 

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Accepted Solutions
bruce_karaffa
Scholar
Scholar
249 Views
Registered: ‎06-21-2017

What can cause timing errors?  Too much logic between registers, poorly design clock domain crossings, incorrect timing constraints among other reasons.  You need to post the timing report and timing constraints.  There is not enough information here to help. 

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1 Reply
bruce_karaffa
Scholar
Scholar
250 Views
Registered: ‎06-21-2017

What can cause timing errors?  Too much logic between registers, poorly design clock domain crossings, incorrect timing constraints among other reasons.  You need to post the timing report and timing constraints.  There is not enough information here to help. 

View solution in original post