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Newbie
Newbie
3,050 Views
Registered: ‎03-27-2017

Timing Errors (intra-clk-path)

Hi guys

 

I have to edit a previous work of a student. But when I open his project, there are a lot of timing errors. So I have to solve them, but I don't know where to start...

I just started programming vhdl and I'm not sure whether I need some buffers or timing constraints to solve those errors. Could you guys give me any hints?

 

This is the timing constraint file:

# ----------------------------------------------------------------------------------------------------------
# Clock definitionen
# ----------------------------------------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS33 [get_ports clk_in1]
#CLK input(generated by the FPGA)
set_property PACKAGE_PIN Y9 [get_ports clk_in1]

# not used because the clk wizard ip block creates his own constraints
#create_clock -period 10.000 -name sysClk -waveform {0.000 5.000} [get_ports clk_in1]

#100 MHz Clock for the devices
create_clock -period 10.000 -name clk_100Mhz -waveform {0.000 5.000} [get_pins EIT_V2_0_i/clk_wiz_0/clk_out1]
# 40 MHz Clock for the adc and the dac spi
create_clock -period 25.000 -name clk_40Mhz -waveform {0.000 12.500} [get_pins EIT_V2_0_i/clk_wiz_0/clk_out2]
#  4 MHz Clock for the main spi
create_clock -period 250.000 -name clk_4Mhz -waveform {0.000 125.000} [get_pins EIT_V2_0_i/clockDivider_0/clkOut]
# ----------------------------------------------------------------------------------------------------------



# ----------------------------------------------------------------------------------------------------------
# input delay
# ----------------------------------------------------------------------------------------------------------
set_input_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports nrst]
set_input_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports miso_adc1]
set_input_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports miso_adc2]

set_input_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports reference]
# ----------------------------------------------------------------------------------------------------------



# ----------------------------------------------------------------------------------------------------------
# Output delay
# ----------------------------------------------------------------------------------------------------------
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports sclk_main]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports {ss_main[0]}]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports {ss_main[1]}]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports {ss_main[2]}]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports mosi_main]

set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports sclk_dac]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports ss_dac]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports mosi_dac]

set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports sclk_adc]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports ss_adc]

set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports {ram_select[0]}]
set_output_delay -clock [get_clocks clk_100Mhz] 0.100 [get_ports {ram_select[1]}]

#HDMI
set_output_delay -clock [get_clocks clk_100Mhz] -max 3.500 [get_ports hd_vsync]
set_output_delay -clock [get_clocks clk_100Mhz] -min -0.200 [get_ports hd_vsync]
set_output_delay -clock [get_clocks clk_100Mhz] -max 3.500 [get_ports hd_hsync]
set_output_delay -clock [get_clocks clk_100Mhz] -min -0.200 [get_ports hd_hsync]
set_output_delay -clock [get_clocks clk_100Mhz] -max 3.500 [get_ports hd_d]
set_output_delay -clock [get_clocks clk_100Mhz] -min -0.200 [get_ports hd_d]
# ----------------------------------------------------------------------------------------------------------

An out-take from the timing analysis:

------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                      WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                      -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk_100Mhz                                                                  -1.078      -15.268                     27                 8541        0.042        0.000                      0                 8541        3.750        0.000                       0                  4267  
clk_40Mhz                                                                   20.563        0.000                      0                  154        0.168        0.000                      0                  154       12.000        0.000                       0                    80  
clk_4Mhz                                                                   245.141        0.000                      0                  104        0.040        0.000                      0                  104      124.500        0.000                       0                    50  
clk_fpga_0                                                                                                                                                                                                               7.845        0.000                       0                     1  
clk_in1                                                                                                                                                                                                                  3.000        0.000                       0                     1  
  clk_out1_EIT_V2_0_clk_wiz_0_0                                                                                                                                                                                          7.845        0.000                       0                     2  
  clk_out2_EIT_V2_0_clk_wiz_0_0                                                                                                                                                                                         22.845        0.000                       0                     2  
  clkfbout_EIT_V2_0_clk_wiz_0_0                                                                                                                                                                                          7.845        0.000                       0                     3  
dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK           22.167        0.000                      0                  531        0.021        0.000                      0                  531       13.750        0.000                       0                   270  
  dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE       57.592        0.000                      0                    1        0.800        0.000                      0                    1       29.500        0.000                       0                     2  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                           To Clock                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                           --------                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
clk_40Mhz                                                            clk_100Mhz                                                                -3.305     -139.451                    126                  126        0.596        0.000                      0                  126  
clk_4Mhz                                                             clk_100Mhz                                                                 0.082        0.000                      0                   84        0.480        0.000                      0                   84  
clk_100Mhz                                                           clk_40Mhz                                                                  0.953        0.000                      0                   21        0.099        0.000                      0                   21  
clk_100Mhz                                                           clk_4Mhz                                                                   3.803        0.000                      0                   23        0.494        0.000                      0                   23  
dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK         56.109        0.000                      0                   18        0.584        0.000                      0                   18  
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1 Reply
Guide
Guide
2,818 Views
Registered: ‎01-23-2009

Re: Timing Errors (intra-clk-path)

In a nutshell, the tools are telling you "With the implementation you have given me, it is not possible to meet the requested timing on these output ports". And it is right...

 

You are using the "slowest" clock insertion mechanism - a pin (I hope a clock pin) going directly to the BUFG. It take 2.334ns to get to the internal flip-flop that generates the output.

 

Next the flip-flop is not packed into the IOB - as a result it has to be routed to the OBUF - this takes 1.663ns.

 

Finally the OBUF is slow - you don't tell us what I/O standard it is, but the fact that it takes 3.546ns indicates that it is a slow I/O standard, possibly with the "SLOW" slew and a low drive strength.

 

You add all these together, and it can't get through the FPGA 3.5ns before the next rising edge of the clock; the period is 10ns and the set_output_delay is 3.5ns, so it needs to do all the above in 6.5ns. It can't.

 

There are a number of things you can do to speed this up:

  - use an MMCM or PLL in the clock input path to remove some of the clock insertion delay

  - force the flip-flop into the IOB

     set_property IOB TRUE [get_ports hd_d[*]]

  - use a faster I/O standard/slew rate/drive strength

 

Avrum

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