01-24-2019 07:52 AM
I am using Vivado 2018.3, Zynq UltraSCALE+ MPSoC 4CG device. I have created a block design which contains Zynq UltraSCALE PS, AXI 1G/2.5G Ethernet IP, AXI_DMA and of course AXI_interconnects.
I have selected 1Gbps as Ethernet Speed and RGMII in Physical Interface selection. Since I have a differential 125 MHz clock, therefore, I am providing 125MHz using Utility Buffer IP and selected IBUFDS to convert from Differential to single ended clock. This single ended clock is fed to gtx_clk of Ethernet Subsystem. The ref_clk of Ethernet Subsystem is fed 333.33 MHz from ZYNQ_PS pl_clk1.
But unfortunately, after the Implementation is complete, it says "Timing Failed". The problem lies in Inter_clock paths Setup Time. I have also attached Failed Timing picture for more clarity. CLK_IN1_D_1_0 is my input clock of 125MHz which can be seen in the attachment. Can someone advise me to improve this so that I can get rid of failed timing?
01-27-2019 09:56 AM
You haven't given us very much data to work with. Ideally we should see both the constraints and the detailed path report of the failing path.
But, this looks like the output constraint on the txd interface. This is a source synchronous (probably) edge aligned output interface. From what little we can see here, it is constrained the "correct" way (see this post on DDR output interfaces and the post referenced within it), which includes a "set_multicycle_path 0" (which is why the requirement of the path is 0).
From what little we can see here, the path seems correct, but is failing by a little bit. Since this is a path to an output pin (and not an internal path - never ignore a violation on an internal path), it may be acceptable to ignore this very minor violation - it is only 82ps, and there is probably a reasonable amount of conservatism in the input requirements of the PHY.
02-06-2019 07:30 AM
Thanks for your reply. I have now attached my constraints file and timing report(.rpx) in attachment. I have seen the posts that you have referenced and I was able to avoid Timing Failure by adding the set_multicycle_path constraint which are mentioned in my target constraints (currently commented out in file).
But the irritating thing for me is that since I am using Integrated IPs from Xilinx and there should be ideally NO timing failure because I have not added anything extra in my block design or in the logic. Is there anything wrong in my configuration or design which is the cause of timing failure? Is it the tool? Is it the 1G/2.5G Ethernet IP?
Please let me know, if you need any other file.
04-08-2019 10:32 AM
Did you ever get a work around for this? I am having timing errors in the exact same way on an Ultrascale+ and the TX clock inter-clock paths. Only have I two MAC cores so I have two sets of errors.