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Observer
Observer
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Registered: ‎02-25-2019

Timing Faliure after Implementation

I started with a simple design using Etherent 1G/2.5G IP , MicroBlaze Processor and UartLIte IP. I used the reference design provided by xilinx in Xapp 1026 for KC705  and Implemented it on VC707 evaluation board. The implementation is complete but there is a timing faliure ,  How do i approach the problem of timing faliure.

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Moderator
Moderator
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Registered: ‎01-16-2013

Hi Amit,

XAPP/TRD are validated for specific to targeted FPGA as you have used XAPP targetted for KC705 with VC707 we need to consider this as custom design and handle the timing for closure.

Can you please validate all the constraints are present? How clock interaction report looks like? Also share the detailed timing report for failing path this will help forum users as well as me to analyze the same and provide the suggestion.

Thanks,
Yash

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