09-27-2007 02:46 AM
09-27-2007 06:09 AM
01-12-2009 02:58 AM
I didn't find a 'magic' solution to the problem I just went through the design and tidied it up.
By this I mean looking for poorly written vhdl & adding in registers into long logic chains.
This process took me 2 or 3 days as I went through every block trying to identify possible weaknesses.
I also trimmed the design to take my gate utilisation down from over 90% to under 80%.
The design is pretty stable now and I can make changes to it without seeing the timing issue.
Best of luck.
01-12-2009 09:37 AM