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Anonymous
Not applicable
14,791 Views

Timing Issue - Clock Distribution

Hi
 
I have a design which meets the only timing constraint that I have in my .ucf file (shown at end of post)
 
The problem that I have is that very small changes like adding a single gate cause major parts of the design to fall over and not operate although the timing constraint is still met.
When I change the design and take out signals to test pins to debug the issue then the timing is changed and the design starts to work again in many cases.
 
At present the design seems stable but I am concerned that the problem will reappear when I have to add functionality to the design.
 
I have my Advanced Map settings set to: Perform Timing-Driven Packing & Placement with Register Duplication and Replicate Logic also enabled.
 
My main clock is used all over the design and at present is showing the following in the clock report
 
+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|        TWO_X_SYSCLK |     BUFGMUX1P| No   | 1451 |  0.264     |  1.265      |
+---------------------+--------------+------+------+------------+-------------+
I am using a CLKDLL with feedback and a BUFG to distribute the clock with minimum skew.
FX2_CLKOUT is the input clock to my design.
TWO_X_SYSCLK  is the output from the CLKDLL
Is there perhaps a way of improving this further by using multiple BUFGs in the clock path?
The implementation tool may do this already, I'm not sure.
 
If anyone has experienced a similar issue before (and managed to correct it) I would appreciate your advice.
 
Also, if there are any other implementation settings or design tips that I should try then please let me know.
 
 
Timing Constraint: (48MHz input clock)
NET "FX2_CLKOUT" TNM_NET = "FX2_CLKOUT";
TIMESPEC "TS_FX2_CLKOUT" = PERIOD "FX2_CLKOUT" 20 ns HIGH 50 %;
 
 
Timing summary:
---------------
Timing errors: 0  Score: 0

Constraints cover 156038 paths, 0 nets, and 29573 connections

Design statistics:
   Minimum period:  16.657ns (Maximum frequency:  60.035MHz)
Many Thanks
 
Dave
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5 Replies
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Professor
Professor
14,784 Views
Registered: ‎08-14-2007

Re: Timing Issue - Clock Distribution

This sort of problem usually indicates that something is not properly constrained.  If all of your logic runs on the same clock, the PERIOD time constraint should prevent problems inside the design, but you could be experiencing problems getting on and off the chip.  If you are not registering all I/O in the IOB's you can have significant setup times on inputs and clock to pin delays on outputs.  You should be able to see the I/O timing in the datasheet section at the end of a detailed post p&r timing report.  Adding constraints to the I/O's can fix the problem with variability.  Also useful is the "Report Uncovered Paths" option in the post p&r static timing report properties.  This may help you to pinpoint the timing problem.

Another helpful tool is the FPGA editor.  Open the FPGA editor for a working version and look at critical component placements like DCM and BUFG's.  Then look at the same placements in a non-working version.  If your problem is due to clock phase, for example, adding LOC constraints to the clock components can give more consistent results.

HTH,
Gabor
-- Gabor
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Anonymous
Not applicable
14,757 Views

Re: Timing Issue - Clock Distribution

Thanks, I will try your suggestions.
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Explorer
Explorer
10,879 Views
Registered: ‎11-13-2007

Re: Timing Issue - Clock Distribution

Did you ever figure out your problem?

 

I'm having the EXACT same issues.

 

 

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Anonymous
Not applicable
10,839 Views

Re: Timing Issue - Clock Distribution

I didn't find a 'magic' solution to the problem I just went through the design and tidied it up.

By this I mean looking for poorly written vhdl &  adding in registers into long logic chains.

This process took me 2 or 3 days as I went through every block trying to identify possible weaknesses.

I also trimmed the design to take my gate utilisation down from over 90% to under 80%. 

The design is pretty stable now and I can make changes to it without seeing the timing issue.

Best of luck.

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Highlighted
Explorer
Explorer
10,834 Views
Registered: ‎11-13-2007

Re: Timing Issue - Clock Distribution

So prior to your general re-working of your code, was there any report that gave you any clues about where to tidy up?
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