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lyuanjie
Observer
Observer
9,907 Views
Registered: ‎10-26-2010

Timing Issues with Virtex-7 FPGA (Register Balancing doesn't seems to work!!!)

I have a few failing path that contains mainly 90% routing delay between one source register to another destination register. Each of these registers resides in different I/O banks, causing the routing to be very long from left to right. To break up these long  critical path, I have added another intermediate register between these two registers. Rather than expecting the timing to be met (with the addition of 1 more clock latency), the ISE Placement tool placed the intermediate register very closer to the destination register. In the end, my timing barely met and the routing between the source register to the intermediate register remained very long. Have anyone encounter such issues before? If so, it would be very kind of you that you can share your design experiences & knowledge. I have used Register Duplication & Balancing setting in ISE and disabled the Removal of equivalent register option. All P&R efforts are normal. The resource utilization is only 1% and Virtex-7 is a really large FPGA. Thanks.

 

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3 Replies
awillen
Mentor
Mentor
9,899 Views
Registered: ‎11-29-2007

Well, did it meet timing? If yes, and you're concerned about repeatability: Set the timing constraint even tighter and see whether the tools can still meet the constraint. If they do, you shouldn't worry about it anymore.



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lyuanjie
Observer
Observer
9,878 Views
Registered: ‎10-26-2010

Hi

 

Thank you for your reply, The timing has improved after I added some pipeline register. But a few paths (about 10) still failed timing. The reason is that it has a routing delay of 5ns from left-center I/O bank to right-top I/O bank in Virtex-7. My target period is 5ns (200MHz). Even when I try to break the path by adding more pipeline register, it does not help and make the timing even worse. To prevent the inference of shift register, I have also manually instantiated two FDCE components. Is there anyway to tell the tool to place this pipeline registers far apart?   

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yashp
Moderator
Moderator
9,871 Views
Registered: ‎01-16-2013

Hello,

 

I have few suggestions for you:

1)      You can manually place the FF. (Pipelined flip flop).

Use LOC constraint for that:

Please refer this link for LOC constraint: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/cgd.pdf (Page # 142)

2)      Or you can open implemented design in FPGA and manually drag and drop that particular FF in favorable slice location.

 

With the help of above two methods you can place pipelined flipflops equidistance.

 

Thanks,

Yash

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