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Visitor
Visitor
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Registered: ‎07-24-2011

Timing Problems with Comparators

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I am trying to compare the outputs of 2 modules. If the comparison is equal the result is a logical AND of the outputs, while if the outputs are not equal then the result is zero. Unfortunately I have a huge problem with the timing paths of the comparators. Here is a small piece of my code:

 

mult_mac_result_1, mult_mac_result_2, spr_dat_mac_1, spr_dat_mac_2 are 32 bit wide

mult_mac_stall_1, mult_mac_stall_2 are 1 bit wide

 

always @(mult_mac_result_1 or mult_mac_result_2 or mult_mac_stall_1 or mult_mac_stall_2 or spr_dat_mac_1 or spr_dat_mac_2)
begin
    if ((((mult_mac_result_1 - mult_mac_result_2) & (spr_dat_mac_1 - spr_dat_mac_2)) != 0) || ((mult_mac_stall_1 - mult_mac_stall_2) != 0)) begin
        mult_freeze <= 1'b1;
    end
    else begin
        mult_mac_result <= mult_mac_result_1 & mult_mac_result_2;
        mult_mac_stall <= mult_mac_stall_1 & mult_mac_stall_2;
        spr_dat_mac <= spr_dat_mac_1 & spr_dat_mac_2;
        mult_freeze <= 1'b0;
    end
end

 

I prefer using substraction instead of equality, and logical addition with wires of the same width, in order to improve the timing performance of the logic (and that happen), but as far as I know the above code is not correct as in the sensitivity list there is no clock at all. Also the tool inform me about this with that warning:
WARNING:Xst:2170 - Unit or1200_qmem_top : the following signal(s) form a combinatorial loop:...

 

My project is in Virtex ML505 board.

My question is how can I improve the timing performance of the comparators (obviously even if I have to rewrite the above code), and how can I implement a fast comparator.

 

Thanks

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Visitor
Visitor
9,630 Views
Registered: ‎07-24-2011

I finally manage to reach the timing requirements of my design by removing the comparators from the critical path.

Thanks all of you for your help and support.

 

Andreas

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Xilinx Employee
Xilinx Employee
9,747 Views
Registered: ‎01-03-2008

 > if ((((mult_mac_result_1 - mult_mac_result_2) & (spr_dat_mac_1 - spr_dat_mac_2)) != 0) || ((mult_mac_stall_1 - mult_mac_stall_2) != 0))

> I prefer using substraction instead of equality,

 

It would appear that you are implementing by a subtractor and a comparator with your code choice.  It is possible that the synthesizer is smarter and converting it back into a comparator instead.

 

if ((( mult_max_result_1 != mult_max_result2) & (spr_dat_mac1 != spr_data_max_2)) | | (mult_mac_stall1 != mult_max_stall2))

 

Is likely to produce better results.

 

> as far as I know the above code is not correct as in the sensitivity list there is no clock

 

Does this section of code need to be registered? If so then you need to change your code to do this.

 

> WARNING:Xst:2170 - Unit or1200_qmem_top : the following signal(s) form a combinatorial loop:...


It would appear that you do in fact need some registers somewhere.  Where the need to go and you know.

 

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Professor
Professor
9,743 Views
Registered: ‎08-14-2007

Actually I don't think Ed's code is equivalent, although it may be closer to what

the OP wanted.  It looks the original code is making a bit-wise and of the two

subtractions.  So the result would only be non-zero if both subtractions had

ones in at least one bit position.  That's not the same as an equality comparitor.

It would be helpful if you posted the complete warning message for the combinatorial

loop.  It should point out the signals.  If you don't see the whole message in

the ISE warnings tab, then you need to find it in the synthesis report file.

 

-- Gabor

-- Gabor
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Xilinx Employee
Xilinx Employee
9,737 Views
Registered: ‎01-03-2008

> Actually I don't think Ed's code is equivalent,

 

Yes, you're right.  If the original code resulted in a 4'b1100 and 4'b0011 the bitwise AND of this would be 4'b0000 and take a different branch than my code.   But this function doesn't match the content in the original post.  Overall very confusing. 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Instructor
Instructor
9,725 Views
Registered: ‎07-21-2009

Because you have assignments in one half of the IF conditional without corresponding assignments in the other half of the IF conditional, you *may* be unintentionally inferring a latch.  Just a guess.

 

Just for grins, what should be the (missing) assignments for these signals:

 

mult_mac_result
mult_mac_stall
spr_dat_mac

 

or are they 'don't care'?  If their values are 'don't care', then assignments for these signals should be moved outside the process where they are now assigned, their assigned values are no longer conditional.

 

P.S.  If I'm wrong on this, don't be shy about saying so.

 

-- Bob Elkind

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2. Search the forums (and search the web) for similar topics.
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Instructor
Instructor
9,723 Views
Registered: ‎07-21-2009

Here is an alternate coding of a 32-bit comparator, also using the fast-adder logic approach:

 

wire [31:0]  operand_A, operand_B;        // the two 32bit operands to be compared

wire [32:0]  A_ext, A_inv, B_ext, B_inv;  // temporary 33bit variables

wire [32:0]  check_A, check_B;  // 33 bit result variables, x[32] is for carry out from x[31]

wire         A_equals_B;        // the final result of the comparator

 

assign A_ext = {1'b0, operand_A};  // extend A to a 33 bit variable, MSB is 0

assign B_ext = {1'b0, operand_B};  // extend B to a 33 bit variable, MSB is 0

assign A_inv = {1'b0, ~operand_A}; // extend 1's complement of A to 33 bit variable, MSB is 0

assign B_inv = {1'b0, ~operand_B}; // extend 1's complement of B to 33 bit variable, MSB is 0

 

assign  check_A = A_ext + B_inv;   // add A to 1s complement of B, bit[32] is carry out

assign  check_B = A_inv + B_ext;   // add 1s complement of A to B, bit[32] is carry out

 

// OR of carry out of both sums, both carry bits are '0' if A=B

assign A_equals_B = ~( check_A[32] | check_B[32] );

 

This implementation has the advantage of a 2-bit result (the two carry out bits) to check for equality.  This is a much simpler logic term than andapo's original implementation.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Tags (2)
Visitor
Visitor
9,706 Views
Registered: ‎07-24-2011

Thank all of you for your answers!!!

 

I implement the design as Bob suggests and the timing results are better that before, but not good enough for my implementation. While my clock with the previous code is working at 29.754ns, now is working at  27.772ns, while at the original design without the comparators is working at 19.923ns.

 

If there is anything else that I can do, please let my know it. Here is my code again for other module which produces more outputs.

 

reg                instfetch_freeze;

wire    [31:0]    if_insn_1;
wire    [31:0]    if_insn_2;
wire  [32:0]    if_insn_1_ext, if_insn_1_inv, if_insn_2_ext, if_insn_2_inv;
wire    [32:0]    check_if_insn_1, check_if_insn_2;
wire                if_insn_1_equals_if_insn_2;

wire    [31:0]    if_pc_1;
wire    [31:0]    if_pc_2;
wire  [32:0]    if_pc_1_ext, if_pc_1_inv, if_pc_2_ext, if_pc_2_inv;
wire    [32:0]    check_if_pc_1, check_if_pc_2;
wire                if_pc_1_equals_if_pc_2;

wire                saving_if_insn_1;
wire                saving_if_insn_2;
wire                if_stall_1;
wire                if_stall_2;
wire                genpc_refetch_1;
wire                genpc_refetch_2;
wire                except_itlbmiss_1;
wire                except_itlbmiss_2;
wire                except_immufault_1;
wire                except_immufault_2;
wire                except_ibuserr_1;
wire                except_ibuserr_2;


// if_insn comparison
assign if_insn_1_ext = {1'b0, if_insn_1};
assign if_insn_2_ext = {1'b0, if_insn_2};
assign if_insn_1_inv = {1'b0, ~if_insn_1};
assign if_insn_2_inv = {1'b0, ~if_insn_2};

assign check_if_insn_1 = if_insn_1_ext + if_insn_2_inv;
assign check_if_insn_2 = if_insn_1_inv + if_insn_2_ext;

assign if_insn_1_equals_if_insn_2 = (check_if_insn_1[32] | check_if_insn_2[32]);


// if_pc comparison
assign if_pc_1_ext = {1'b0, if_pc_1};
assign if_pc_2_ext = {1'b0, if_pc_2};
assign if_pc_1_inv = {1'b0, ~if_pc_1};
assign if_pc_2_inv = {1'b0, ~if_pc_2};

assign check_if_pc_1 = if_pc_1_ext + if_pc_2_inv;
assign check_if_pc_2 = if_pc_1_inv + if_pc_2_ext;

assign if_pc_1_equals_if_pc_2 = (check_if_pc_1[32] | check_if_pc_2[32]);


always @(if_insn_1_equals_if_insn_2 or if_pc_1_equals_if_pc_2 or saving_if_insn_1 or saving_if_insn_2 or if_stall_1 or if_stall_2 or genpc_refetch_1 or genpc_refetch_2 or except_itlbmiss_1 or except_itlbmiss_2 or except_immufault_1 or except_immufault_2 or except_ibuserr_1 or except_ibuserr_2)
begin
    if ((if_insn_1_equals_if_insn_2 != 0) || (if_pc_1_equals_if_pc_2 !=0) || (((saving_if_insn_1 - saving_if_insn_2) & (if_stall_1 - if_stall_2) & (genpc_refetch_1 - genpc_refetch_2) & (except_itlbmiss_1 - except_itlbmiss_2) & (except_immufault_1 - except_immufault_2) & (except_ibuserr_1 - except_ibuserr_2)) !=0)) begin
        if_insn <= 32'b0;
        if_pc <= 32'b0;
        saving_if_insn <= 1'b0;
        if_stall <= 1'b0;
        genpc_refetch <= 1'b0;
        except_itlbmiss <= 1'b0;
        except_immufault <= 1'b0;
        except_ibuserr <= 1'b0;
        instfetch_freeze <= 1'b1;
    end
    else begin
        if_insn <= if_insn_1 & if_insn_2;
        if_pc <= if_pc_1 & if_pc_2;
        saving_if_insn <= saving_if_insn_1 & saving_if_insn_2;
        if_stall <= if_stall_1 & if_stall_2;
        genpc_refetch <= genpc_refetch_1 & genpc_refetch_2;
        except_itlbmiss <= except_itlbmiss_1 & except_itlbmiss_2;
        except_immufault <= except_immufault_1 & except_immufault_2;
        except_ibuserr <= except_ibuserr_1 & except_ibuserr_2;
        instfetch_freeze <= 1'b0;
    end
end


And here is the complete warning message:

WARNING:Xst:2170 - Unit or1200_qmem_top : the following signal(s) form a combinatorial loop: or1200_cpu/Madd_check_if_insn_2_cy<14>, or1200_cpu/Madd_check_if_insn_2_cy<8>, or1200_genpc/icpu_adr_o_and0000, or1200_immu_top/icpu_adr_i<13>, or1200_cpu/genpc_refetch, or1200_cpu/icpu_adr_o<13>, or1200_cpu/Madd_check_if_insn_2_cy<15>, or1200_cpu/Madd_check_if_insn_2_cy<20>, or1200_immu_top/icpu_cycstb_i, or1200_freeze/genpc_freeze, or1200_if_2/saving_if_insn, or1200_freeze/id_freeze, or1200_top/icpu_adr
_cpu<13>, or1200_except/except_trig<1>, or1200_cpu/Madd_check_if_insn_2_cy<30>, or1200_freeze/saving_if_insn, or1200_cpu/if_stall, or1200_cpu/Madd_check_if_insn_2_cy<24>, or1200_immu_top/page_cross, or1200_cpu/instfetch_freeze, or1200_cpu/saving_if_insn, or1200_immu_top/Mcompar_page_cross_cy<4>, or1200_except/except_type_or0000, or1200_genpc/icpu_cycstb_o, or1200_cpu/Madd_check_if_insn_2_cy<4>, or1200_immu_top/fault, or1200_cpu/Madd_check_if_insn_2_cy<17>, qmemimmu_cycstb_i, or1200_immu_top/Mcomp
ar_page_cross_cy<0>, or1200_immu_top/Mcompar_page_cross_cy<1>, or1200_immu_top/Mcompar_page_cross_cy<2>, or1200_if_2/if_flushpipe, or1200_immu_top/qmemimmu_cycstb_o, or1200_top/icpu_err_immu, or1200_cpu/Madd_check_if_insn_2_cy<5>, or1200_if_2/if_stall, or1200_cpu/Madd_check_if_insn_2_cy<27>, or1200_cpu/Madd_check_if_insn_2_cy<10>, or1200_genpc/icpu_adr_o<13>, or1200_except/ex_freeze, or1200_cpu/if_stall_2, or1200_cpu/Madd_check_if_insn_2_cy<21>, or1200_ctrl/except_flushpipe, or1200_genpc/genpc_fr
eeze, or1200_freeze/ex_freeze, or1200_cpu/Madd_check_if_insn_2_cy<0>, or1200_if_2/N14, or1200_cpu/saving_if_insn_2, or1200_cpu/Madd_check_if_insn_2_cy<31>, or1200_cpu/except_flushpipe, or1200_cpu/icpu_err_i, or1200_cpu/Madd_check_if_insn_2_cy<2>, or1200_cpu/Madd_check_if_insn_2_cy<16>, or1200_ctrl/id_flushpipe, or1200_cpu/Madd_check_if_insn_2_cy<18>, or1200_immu_top/icpu_err_o, or1200_cpu/Madd_check_if_insn_2_cy<22>, or1200_cpu/Madd_check_if_insn_2_cy<13>, or1200_cpu/Madd_check_if_insn_2_cy<29>,
or1200_except/except_flushpipe, or1200_cpu/Madd_check_if_insn_2_cy<7>, or1200_cpu/genpc_freeze, or1200_cpu/Madd_check_if_insn_2_cy<6>, or1200_cpu/if_insn_2<0>, or1200_cpu/Madd_check_if_insn_2_cy<26>, or1200_if_2/if_insn<0>, or1200_cpu/Madd_check_if_insn_2_cy<9>, or1200_except/N117, or1200_cpu/Madd_check_if_insn_2_cy<28>, or1200_cpu/Madd_check_if_insn_2_cy<11>, or1200_freeze/if_stall, or1200_cpu/Madd_check_if_insn_2_cy<1>, or1200_cpu/Madd_check_if_insn_2_cy<23>, or1200_cpu/Madd_check_if_insn_2_cy<
25>, or1200_genpc/genpc_refetch, or1200_if_2/icpu_err_i, or1200_cpu/if_flushpipe, or1200_cpu/Madd_check_if_insn_2_cy<3>, or1200_immu_top/Mcompar_page_cross_cy<5>, or1200_cpu/icpu_cycstb_o, or1200_immu_top/Mcompar_page_cross_lut<0>, or1200_top/qmemimmu_cycstb_immu, or1200_cpu/Madd_check_if_insn_2_cy<12>, or1200_cpu/ex_freeze, or1200_cpu/Madd_check_if_insn_2_cy<19>, or1200_top/icpu_cycstb_cpu, or1200_immu_top/Mcompar_page_cross_cy<3>.

 

Andreas

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Instructor
Instructor
9,696 Views
Registered: ‎07-21-2009

Andreas,

 

Are you allergic to comments in your code?

Have you simulated the new code, and does it work as expected?

 

In these lines of the code you posted:

assign if_pc_1_equals_if_pc_2 = (check_if_pc_1[32] | check_if_pc_2[32]);

assign if_insn_1_equals_if_insn_2 = (check_if_insn_1[32] | check_if_insn_2[32]);

 

In both lines, the result is '0' if the two values are matched, '1' if they differ.

 

If you want help on reducing the critical path in your design, you will need to provide details of how the inputs to your code snippet are generated.  I suspect that the comparator prop delay is quite a bit less than 27nS.  If so, then the bulk of the path delay is yet a mystery which cannot be explained by your code snippet.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Professor
Professor
9,692 Views
Registered: ‎08-14-2007

Are you allergic to comments in your code?

 

I'm sure the comments were stripped out before posting to reduce the forum traffic bandwidth :smileywink:

-- Gabor
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Visitor
Visitor
9,681 Views
Registered: ‎07-24-2011

Are you allergic to comments in your code?

Sorry but I never put comments while I am writing a small piece of code, until the code reaches its final form.Sorry again.

 

Have you simulated the new code, and does it work as expected?

Yes, the simulation is OK.

 

In these lines of the code you posted:

assign if_pc_1_equals_if_pc_2 = (check_if_pc_1[32] | check_if_pc_2[32]);

assign if_insn_1_equals_if_insn_2 = (check_if_insn_1[32] | check_if_insn_2[32]);

 

In both lines, the result is '0' if the two values are matched, '1' if they differ.

Yes I know that. I just made a small change of your code.

 

If you want help on reducing the critical path in your design, you will need to provide details of how the inputs to your code snippet are generated.  I suspect that the comparator prop delay is quite a bit less than 27nS.  If so, then the bulk of the path delay is yet a mystery which cannot be explained by your code snippet.

I think that the delay is the acctually the difference between 27.772ns (current speed) and 19.923ns (the design without the comparators) = 7,849 ns. Is that correct?

If I can gine you more details about my design in order to help me solve my problem, please tell me what these details are.

 

The only output that I have in mind know is the slower path as discribed from the Post-Par Static Timing Report:


Paths for end point or1200_top/or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/Mram_mem7_RAMA (SLICE_X24Y73.CE), 10028806580 paths
--------------------------------------------------------------------------------
Slack (setup path):     -7.772ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff2q (FF)
  Destination:          or1200_top/or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/Mram_mem7_RAMA (RAM)
  Requirement:          20.000ns
  Data Path Delay:      27.505ns (Levels of Logic = 42)
  Clock Path Skew:      -0.142ns (1.154 - 1.296)
  Source Clock:         wb_clk rising at 0.000ns
  Destination Clock:    wb_clk rising at 20.000ns
  Clock Uncertainty:    0.125ns

  Clock Uncertainty:          0.125ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.180ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff2q to or1200_top/or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/Mram_mem7_RAMA
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y85.CQ      Tcko                  0.471   dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff2
                                                       dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff2q
    SLICE_X25Y85.A3      net (fanout=4)        0.596   dbg_top/i_dbg_wb/wb_biu_i/str_sync_wbff2q
    SLICE_X25Y85.A       Tilo                  0.094   dbg_top/i_dbg_wb/wb_biu_i/wb_fsm_state
                                                       dbg_top/i_dbg_wb/wb_biu_i/wb_stb_o1
    SLICE_X19Y83.B6      net (fanout=6)        0.520   wb_dm_cyc_o
    SLICE_X19Y83.B       Tilo                  0.094   tc_top/t18_ch_upper/req_r<5>
                                                       tc_top/t18_ch_upper/req_i_3_and0000
    SLICE_X17Y83.C1      net (fanout=3)        0.863   tc_top/t18_ch_upper/req_i<3>
    SLICE_X17Y83.C       Tilo                  0.094   tc_top/t18_ch_upper/req_r<4>
                                                       tc_top/t18_ch_upper/req_won<4>1
    SLICE_X18Y83.D3      net (fanout=84)       0.714   tc_top/t18_ch_upper/req_won<4>
    SLICE_X18Y83.D       Tilo                  0.094   tc_top/z_wb_cyc_i
                                                       tc_top/t18_ch_upper/t0_out<70>1
    SLICE_X19Y84.C2      net (fanout=3)        0.776   tc_top/z_wb_cyc_i
    SLICE_X19Y84.C       Tilo                  0.094   tc_top/t18_ch_lower/req_t<3>
                                                       tc_top/t18_ch_lower/req_t_1_and000011
    SLICE_X16Y86.A3      net (fanout=47)       0.772   tc_top/t18_ch_lower/N2
    SLICE_X16Y86.A       Tilo                  0.094   tc_top/z_wb_dat_t<17>
                                                       tc_top/t18_ch_lower/req_t_1_and00002
    SLICE_X19Y84.B2      net (fanout=34)       0.893   tc_top/t18_ch_lower/req_t<1>
    SLICE_X19Y84.B       Tilo                  0.094   tc_top/t18_ch_lower/req_t<3>
                                                       tc_top/t18_ch_lower/i0_out<0>
    SLICE_X17Y83.D6      net (fanout=3)        0.451   tc_top/z_wb_err_t
    SLICE_X17Y83.D       Tilo                  0.094   tc_top/t18_ch_upper/req_r<4>
                                                       tc_top/t18_ch_upper/i4_out<0>1
    SLICE_X24Y82.A6      net (fanout=1)        0.645   tc_top/yi4_wb_err_o
    SLICE_X24Y82.A       Tilo                  0.094   wb_rim_dat_i<5>
                                                       tc_top/i4_wb_err_o1
    SLICE_X31Y78.A6      net (fanout=8)        0.922   wb_rdm_err_i
    SLICE_X31Y78.A       Tilo                  0.094   or1200_top/dcsb_ack_sb
                                                       or1200_top/dwb_biu/biu_ack_o1
    SLICE_X32Y71.C6      net (fanout=27)       0.651   or1200_top/dcsb_ack_sb
    SLICE_X32Y71.C       Tilo                  0.094   or1200_top/or1200_dc_top/dcfsm_first_miss_ack
                                                       or1200_top/or1200_dc_top/or1200_dc_fsm/load_miss_ack1
    SLICE_X32Y71.D5      net (fanout=2)        0.263   or1200_top/or1200_dc_top/or1200_dc_fsm/load_miss_ack
    SLICE_X32Y71.D       Tilo                  0.094   or1200_top/or1200_dc_top/dcfsm_first_miss_ack
                                                       or1200_top/or1200_dc_top/or1200_dc_fsm/first_miss_ack1
    SLICE_X30Y70.C6      net (fanout=34)       0.489   or1200_top/or1200_dc_top/dcfsm_first_miss_ack
    SLICE_X30Y70.C       Tilo                  0.094   or1200_top/dcpu_rty_qmem
                                                       or1200_top/or1200_dc_top/dcqmem_ack_o1
    SLICE_X30Y68.A6      net (fanout=6)        0.327   or1200_top/dcpu_ack_qmem
    SLICE_X30Y68.A       Tilo                  0.094   or1200_top/or1200_cpu/lsu_stall
                                                       or1200_top/or1200_cpu/or1200_lsu/lsu_stall2
    SLICE_X30Y69.A6      net (fanout=4)        0.321   or1200_top/dcpu_cycstb_cpu
    SLICE_X30Y69.A       Tilo                  0.094   or1200_top/dcqmem_cycstb_qmem
                                                       or1200_top/or1200_dmmu_top/qmemdmmu_cycstb_o1
    SLICE_X31Y70.A6      net (fanout=11)       0.305   or1200_top/dcqmem_cycstb_qmem
    SLICE_X31Y70.A       Tilo                  0.094   or1200_top/or1200_dc_top/dcfsm_first_miss_err
                                                       or1200_top/or1200_dc_top/or1200_dc_fsm/first_miss_err1
    SLICE_X30Y70.B6      net (fanout=2)        0.308   or1200_top/or1200_dc_top/dcfsm_first_miss_err
    SLICE_X30Y70.B       Tilo                  0.094   or1200_top/dcpu_rty_qmem
                                                       or1200_top/or1200_dc_top/dcqmem_tag_o<0>1
    SLICE_X34Y66.B5      net (fanout=1)        0.577   or1200_top/dcqmem_tag_dc<0>
    SLICE_X34Y66.B       Tilo                  0.094   or1200_top/dcqmem_ci_qmem
                                                       or1200_top/or1200_dmmu_top/dcpu_tag_o<0>1
    SLICE_X32Y65.C4      net (fanout=3)        0.649   or1200_top/dcpu_tag_dmmu<0>
    SLICE_X32Y65.C       Tilo                  0.094   or1200_top/or1200_cpu/except_dtlbmiss
                                                       or1200_top/or1200_cpu/or1200_lsu/except_dtlbmiss1
    SLICE_X28Y63.D5      net (fanout=4)        0.695   or1200_top/or1200_cpu/except_dtlbmiss
    SLICE_X28Y63.D       Tilo                  0.094   or1200_top/or1200_cpu/abort_ex
                                                       or1200_top/or1200_cpu/or1200_except/abort_ex
    SLICE_X27Y58.B5      net (fanout=2)        0.835   or1200_top/or1200_cpu/abort_ex
    SLICE_X27Y58.B       Tilo                  0.094   or1200_top/ex_freeze
                                                       or1200_top/or1200_cpu/or1200_freeze/ex_freeze1
    SLICE_X32Y62.B6      net (fanout=69)       1.063   or1200_top/ex_freeze
    SLICE_X32Y62.B       Tilo                  0.094   or1200_top/or1200_cpu/spr_dat_ppc<13>
                                                       or1200_top/or1200_cpu/or1200_except/except_trig_and00071
    SLICE_X27Y63.A5      net (fanout=40)       0.950   or1200_top/or1200_cpu/or1200_except/except_trig<6>
    SLICE_X27Y63.A       Tilo                  0.094   or1200_top/or1200_cpu/id_pc<17>
                                                       or1200_top/or1200_cpu/or1200_except/except_type_or000047
    SLICE_X27Y63.B6      net (fanout=42)       0.242   or1200_top/or1200_cpu/or1200_except/except_type_or0000
    SLICE_X27Y63.B       Tilo                  0.094   or1200_top/or1200_cpu/id_pc<17>
                                                       or1200_top/or1200_cpu/or1200_except/except_flushpipe1
    SLICE_X16Y62.B6      net (fanout=142)      0.679   or1200_top/or1200_cpu/except_flushpipe
    SLICE_X16Y62.B       Tilo                  0.094   or1200_top/or1200_cpu/alu_op<2>
                                                       or1200_top/or1200_cpu/or1200_ctrl/id_flushpipe1
    SLICE_X20Y76.C5      net (fanout=170)      1.103   or1200_top/or1200_cpu/ex_flushpipe
    SLICE_X20Y76.C       Tilo                  0.094   or1200_top/or1200_cpu/if_insn_2<31>
                                                       or1200_top/or1200_cpu/or1200_if_2/if_insn<0>111
    SLICE_X11Y73.C6      net (fanout=28)       0.753   or1200_top/or1200_cpu/or1200_if_2/N14
    SLICE_X11Y73.C       Tilo                  0.094   or1200_top/or1200_cpu/if_insn_1<2>
                                                       or1200_top/or1200_cpu/or1200_if_2/if_insn<2>1
    SLICE_X15Y72.C5      net (fanout=4)        0.580   or1200_top/or1200_cpu/if_insn_2<2>
    SLICE_X15Y72.COUT    Topcyc                0.423   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<3>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_lut<2>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<3>
    SLICE_X15Y73.CIN     net (fanout=1)        0.000   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<3>
    SLICE_X15Y73.COUT    Tbyp                  0.104   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<7>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<7>
    SLICE_X15Y74.CIN     net (fanout=1)        0.000   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<7>
    SLICE_X15Y74.COUT    Tbyp                  0.104   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<11>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<11>
    SLICE_X15Y75.CIN     net (fanout=1)        0.000   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<11>
    SLICE_X15Y75.COUT    Tbyp                  0.104   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<15>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<15>
    SLICE_X15Y76.CIN     net (fanout=1)        0.000   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<15>
    SLICE_X15Y76.COUT    Tbyp                  0.104   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<19>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<19>
    SLICE_X15Y77.CIN     net (fanout=1)        0.000   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<19>
    SLICE_X15Y77.COUT    Tbyp                  0.104   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<23>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<23>
    SLICE_X15Y78.CIN     net (fanout=1)        0.000   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<23>
    SLICE_X15Y78.COUT    Tbyp                  0.104   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<27>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<27>
    SLICE_X15Y79.CIN     net (fanout=1)        0.000   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<27>
    SLICE_X15Y79.DMUX    Tcind                 0.330   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<31>
                                                       or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<31>
    SLICE_X15Y71.A5      net (fanout=1)        0.750   or1200_top/or1200_cpu/Madd_check_if_insn_1_cy<31>
    SLICE_X15Y71.A       Tilo                  0.094   or1200_top/or1200_cpu/if_insn<10>
                                                       or1200_top/or1200_cpu/if_insn_or00001
    SLICE_X15Y71.B6      net (fanout=71)       0.274   or1200_top/or1200_cpu/instfetch_freeze
    SLICE_X15Y71.B       Tilo                  0.094   or1200_top/or1200_cpu/if_insn<10>
                                                       or1200_top/or1200_cpu/saving_if_insn1
    SLICE_X24Y68.B6      net (fanout=1)        0.674   or1200_top/or1200_cpu/saving_if_insn
    SLICE_X24Y68.B       Tilo                  0.094   or1200_top/or1200_cpu/or1200_freeze/waiting_on<1>
                                                       or1200_top/or1200_cpu/or1200_freeze/genpc_freeze1
    SLICE_X21Y68.A6      net (fanout=3)        0.305   or1200_top/or1200_cpu/genpc_freeze
    SLICE_X21Y68.A       Tilo                  0.094   or1200_top/or1200_cpu/or1200_genpc/pc<6>7
                                                       or1200_top/or1200_cpu/or1200_genpc/icpu_cycstb_o1
    SLICE_X22Y68.A6      net (fanout=3)        0.301   or1200_top/icpu_cycstb_cpu
    SLICE_X22Y68.A       Tilo                  0.094   or1200_top/or1200_immu_top/spr_dat_reg<20>
                                                       or1200_top/or1200_immu_top/itlb_en1
    SLICE_X17Y70.B6      net (fanout=2)        0.515   or1200_top/or1200_immu_top/itlb_en
    SLICE_X17Y70.B       Tilo                  0.094   or1200_top/or1200_immu_top/or1200_immu_tlb/tlb_index<1>
                                                       or1200_top/or1200_immu_top/or1200_immu_tlb/tlb_tr_en1
    SLICE_X19Y67.A6      net (fanout=3)        0.461   or1200_top/or1200_immu_top/or1200_immu_tlb/tlb_tr_en
    SLICE_X19Y67.A       Tilo                  0.094   or1200_top/or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/addr_reg<3>
                                                       or1200_top/or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/_and00001
    SLICE_X24Y73.CE      net (fanout=8)        0.738   or1200_top/or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/_and0000
    SLICE_X24Y73.CLK     Tceck                 0.501   or1200_top/or1200_immu_top/itlb_ppn<30>
                                                       or1200_top/or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/Mram_mem7_RAMA
    -------------------------------------------------  ---------------------------
    Total                                     27.505ns (5.545ns logic, 21.960ns route)
                                                       (20.2% logic, 79.8% route)

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Instructor
Instructor
6,824 Views
Registered: ‎07-21-2009

Are you allergic to comments in your code?

Sorry but I never put comments while I am writing a small piece of code, until the code reaches its final form.Sorry again.

Providing comments with your code is a small price to pay.  You might get more help from strangers with a bit of help for them.

 

If you want help on reducing the critical path in your design, you will need to provide details of how the inputs to your code snippet are generated.  I suspect that the comparator prop delay is quite a bit less than 27nS.  If so, then the bulk of the path delay is yet a mystery which cannot be explained by your code snippet.

If I can gine you more details about my design in order to help me solve my problem, please tell me what these details are.

Please check the highlighted words.

 

I think that the delay is the acctually the difference between 27.772ns (current speed) and 19.923ns (the design without the comparators) = 7,849 ns. Is that correct?

 

If the comparator delay is roughly 8nS, you might be better off with a simple 3-stage or 4-stage XNOR-AND comparator.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Visitor
Visitor
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Registered: ‎07-24-2011

I finally manage to reach the timing requirements of my design by removing the comparators from the critical path.

Thanks all of you for your help and support.

 

Andreas

View solution in original post

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Instructor
Instructor
6,804 Views
Registered: ‎07-21-2009

Please mark this thread as 'solved'.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher
Teacher
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Registered: ‎09-09-2010
"Sorry but I never put comments while I am writing a small piece of code, until the code reaches its final form."

The comments are the FIRST thing you should write, describing what the code module is trying to do!

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor
Visitor
6,785 Views
Registered: ‎07-24-2011

OK The next time I will put comments in my code in order to help for the answer.

 

Thanks again

Andreas

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Professor
Professor
6,778 Views
Registered: ‎08-14-2007

1) Comments in the code help you organize your thoughts so you can come up with your own answers.

 

2) Comments in your code help you remember what you were thinking when you wrote the code, so

you can make changes much later without unintentionally messing up the original intent.

 

3) And finally comments help others to understand what the code does and how, in case you're

not the one in charge of maintaining it.

 

Note that the first two reasons for comments are to help yourself...

 

Regards,

Gabor

-- Gabor
Instructor
Instructor
6,776 Views
Registered: ‎07-21-2009

3) And finally comments help others to understand what the code does and how, in case you're not the one in charge of maintaining it.

And if you believe in the value of design reviews, design documentation, or design collaboration -- comments are helpful there as well.  A good, solid design review helps everyone -- including the designer.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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