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Visitor
Visitor
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Registered: ‎03-05-2019

Timing Pulses in nano second pulses.

Dear Sirs,

I want to generate Pulses in 1nS steps like 999nS, 1000nS, 1001nS?

is it possible on Zynq ZC702 Evaluation board.

regards

Sandip

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Guide
Guide
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Registered: ‎01-23-2009

This is a pretty open question.

I presume you are talking about an signal coming out of the FPGA? What I/O standard are you planning to use?

The answer is at least "sort of". Using a 500MHz clock and an OSERDES in DDR mode you can generate an outgoing bit stream at 1G samples/second. By controlling the input to the OSERDES (which you would need to do at a lower frequency - say 4 bits at 250MHz) you can generate any outgoing pattern.

But you also have physical limitations. The I/O cannot respond instantaneously - depending on the I/O standard used, you will have rise times and fall times that are longer than 1ns. So trying to send a 1ns pulse will likely result in nothing more than a glitch - i.e. a partial transition from 0-1 then back to 0. But, on larger pulses, a sequence of 1000 1's in a row will be around 1ns longer than a sequence of 999 1's in a row.

Avrum

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Voyager
Voyager
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Registered: ‎05-11-2015

 

Just adding to @avrumw 's answer that if you need accuracy for those pulses you'll need a properly fast driver. Taming the nanoseconds is only easy in the whiteboards where signals are perfectly square.

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