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Visitor mbhardware
Visitor
6,710 Views
Registered: ‎03-26-2009

Timing Report: Requirement 0.0 ns - is that correct?

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Hello,

in my timing report I get some (hold) violations. I'm wondering that the Xilinx-Tool (ISE 10.1) requires 0.0 ns between two FFs.
In the report I found:

Requirement: 0.000 ns

I think the problem is, that I change the clock domain. The first FF is driven with the double clock frequency (clk2x) and the second FF with clk1x.
The clocks are derived by using a DCM and in the UCF I set a PERIOD constraint.

So my question:
- Is the requirement of 0.0 ns correct?
- Or in general, what is the meaning of this requirement?
- Can I define a constraint for example:

NET "interconnect_between_two_ff" MAXDELAY = 10 ns;


when period of clk2x is 10 ns and period of clk1x is 20 ns?

 

(Because sometimes I got in the report: "Requirement: 10.0 ns" and sometimes "Requirement: 0.0 ns"?! 



Thank you

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1 Solution

Accepted Solutions
Instructor
Instructor
7,965 Views
Registered: ‎08-14-2007

Re: Timing Report: Requirement 0.0 ns - is that correct?

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I think you are confusing hold time and setup time.  10 ns would be a setup time

requirement - time from one clock to the next clock.  0.0 ns is a hold time

requirement which compares the relative delay of data and clock.  Normally

when both flip-flops  are on the same global clock net you don't get hold

violations because the clock skew is near zero and the minimum data delay

is significantly more than the clock skew.  When using two related clocks,

you need to be sure that the minimum data delay exceeds the clock skew.

"Hold time" is considered zero when the data changes at exactly the same

time as the clock at the receiving end of the path.

 

Regards,

Gabor

-- Gabor
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2 Replies
Instructor
Instructor
7,966 Views
Registered: ‎08-14-2007

Re: Timing Report: Requirement 0.0 ns - is that correct?

Jump to solution

I think you are confusing hold time and setup time.  10 ns would be a setup time

requirement - time from one clock to the next clock.  0.0 ns is a hold time

requirement which compares the relative delay of data and clock.  Normally

when both flip-flops  are on the same global clock net you don't get hold

violations because the clock skew is near zero and the minimum data delay

is significantly more than the clock skew.  When using two related clocks,

you need to be sure that the minimum data delay exceeds the clock skew.

"Hold time" is considered zero when the data changes at exactly the same

time as the clock at the receiving end of the path.

 

Regards,

Gabor

-- Gabor
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Visitor mbhardware
Visitor
6,699 Views
Registered: ‎03-26-2009

Re: Timing Report: Requirement 0.0 ns - is that correct?

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Thank you so much.

 

Now I will try to delay the second (slow) clock (phase shift), so that it is not synchronous to the first one. 

 

Greets

michael 

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