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anjaneyulu.challa9
Adventurer
Adventurer
1,776 Views
Registered: ‎04-11-2017

Timing Warnings in methodology DRC report

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I have a design which meets the timing for 20 mhz frequency.

 

 

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     11.927        0.000                      0               110952        0.053        0.000                      0               110952        1.100        0.000                       0                 42592  


All user specified timing constraints are met.

 

I am seeing some warnings related to timing in methodology drc report

 

 

TIMING-17#65 Warning
Non-clocked sequential cell  
The clock pin xxxx/xxxxx/xxxx/u_rx/clk is not reached by a timing clock
Related violations: <none>

TIMING-17#66 Warning
Non-clocked sequential cell  
The clock pin xxxx/xxxxx/xxxx/int_reg/C is not reached by a timing clock
Related violations: <none>

After going through the vivado-design-analysis and closure techniques [UG906] I understood that this warnings are because the corresponding clock pin is not constrained properly. In my case it is a div2 of the main clock generated from the mmcm which goes to all the other IP's in the design. Ideally there must be a generated clock at the div2 module but there are no such generated clocks in my constraints file(though the timing has met ). What happens if generated clocks are not provided to vivado ? Does it do the timing analysis with the actual clock or the div 2 clock or makes the path as false path for timing analysis ?

 

 

Since my design has met the timing can I use it on the hardware without any issue ?

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avrumw
Guide
Guide
1,914 Views
Registered: ‎01-23-2009

What happens if generated clocks are not provided to vivado ? ... Since my design has met the timing can I use it on the hardware without any issue ?

 

No.

 

If any cell has a "no_clock" warning in the check_timing report, that means (literally) that there is no clock defined on that clocked cell. Since there is no clock, there are no timing checks done - it simply does not do setup or hold checks on paths that start or end at that flip-flop. Since no timing checks are done, it is impossible to fail timing, so the TNS is essentially meaningless.

 

That being said, what you are describing doesn't make sense. If you have an MMCM in your design, and you have a "create_clock" on the input port of the design (that drives the MMCM's CLKIN), then the tool will automatically generate correct clocks on all the MMCM outputs - an explicit create_generated_clock is not needed (and is not recommended). So, this "div2" clock out of the MMCM should already be constrained as long as the input clock is constrained. Even if you haven't explicitly constrained the input clock, if you used the clocking wizard to generate the MMCM, then the wizard will have constrained the input clock for you...

 

So you need to figure out why this clock isn't constrained - if it really was the output of the MMCM, it should have been. You need to check your clock connectivity to make sure that this endpoint is really connected to the MMCM output (via a clock buffer). This can easily be done in the schematic generator - generate a schematic of the offending flip-flop, and then double click on the clock pin - this will trace it backwards. You can continue this way until you reach the MMCM (via the clock buffer)....

 

Avrum

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1 Reply
avrumw
Guide
Guide
1,915 Views
Registered: ‎01-23-2009

What happens if generated clocks are not provided to vivado ? ... Since my design has met the timing can I use it on the hardware without any issue ?

 

No.

 

If any cell has a "no_clock" warning in the check_timing report, that means (literally) that there is no clock defined on that clocked cell. Since there is no clock, there are no timing checks done - it simply does not do setup or hold checks on paths that start or end at that flip-flop. Since no timing checks are done, it is impossible to fail timing, so the TNS is essentially meaningless.

 

That being said, what you are describing doesn't make sense. If you have an MMCM in your design, and you have a "create_clock" on the input port of the design (that drives the MMCM's CLKIN), then the tool will automatically generate correct clocks on all the MMCM outputs - an explicit create_generated_clock is not needed (and is not recommended). So, this "div2" clock out of the MMCM should already be constrained as long as the input clock is constrained. Even if you haven't explicitly constrained the input clock, if you used the clocking wizard to generate the MMCM, then the wizard will have constrained the input clock for you...

 

So you need to figure out why this clock isn't constrained - if it really was the output of the MMCM, it should have been. You need to check your clock connectivity to make sure that this endpoint is really connected to the MMCM output (via a clock buffer). This can easily be done in the schematic generator - generate a schematic of the offending flip-flop, and then double click on the clock pin - this will trace it backwards. You can continue this way until you reach the MMCM (via the clock buffer)....

 

Avrum

View solution in original post