UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
396 Views
Registered: ‎06-26-2019

Timing analyzer problem

Hi, I have recently design a Schemtic in xilinx ISE14.7 version.But, before that i need to use XC9500 CPLD's obsolete family & shown a problem in the timing analyzer. i just attach a screenshot with this message . Please provide a sugggestion to solve this problem.
PROBLEM IN THE TIMING ANALYSER.png
0 Kudos
7 Replies
Xilinx Employee
Xilinx Employee
362 Views
Registered: ‎05-14-2008

Re: Timing analyzer problem

Is this a show-stop problem?

Looks like a warning. Fit completed successfully, didn't it?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
352 Views
Registered: ‎06-26-2019

Re: Timing analyzer problem

Yes, some other problem.

But its fine.

I have one more doudt 

We are designing a schematic in Xilinx ISE 14.7 Version. So, now we are facing an issue in our design. In our previous design there is a symbol called “BUFE” But, in Xilinx 14.7 there is no such a symbol.

 

So, can you please suggest alternating symbol for BUFE.

0 Kudos
Xilinx Employee
Xilinx Employee
332 Views
Registered: ‎05-14-2008

Re: Timing analyzer problem

Are you targeting CPLD or any other device?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
325 Views
Registered: ‎06-26-2019

Re: Timing analyzer problem

Hi,

We are curently designing for Spartan 6 board.

 

Regards,

Mohammed Aboo Saleh

0 Kudos
Xilinx Employee
Xilinx Employee
298 Views
Registered: ‎05-14-2008

Re: Timing analyzer problem

Spartan6 does not have BUFE component.

It has BUFG, BUFIO2, BUFPLL, BUFH.

Usually we use BUFG.

For details about clock resources, please refer to UG382.

-vivian

 

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
289 Views
Registered: ‎06-26-2019

Re: Timing analyzer problem

Hi,

BUFE Means buffer with enable it is also active High enable.

BUFG is a simple buffer.

So, can any other symbol can replace exact BUFE operation.

 

Regards,

Mohammed Aboo Saleh

0 Kudos
Xilinx Employee
Xilinx Employee
282 Views
Registered: ‎05-14-2008

Re: Timing analyzer problem

BUFG is actually one of the configurations of BUFGCTRL.

BUFGCTRL can be configured as BUFGCE.

I believe BUFGCE is what you need.

You can find the answer you need in UG382.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos