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497 Views
Registered: ‎06-26-2019

Timing analyzer problem

Hi, I have recently design a Schemtic in xilinx ISE14.7 version.But, before that i need to use XC9500 CPLD's obsolete family & shown a problem in the timing analyzer. i just attach a screenshot with this message . Please provide a sugggestion to solve this problem.
PROBLEM IN THE TIMING ANALYSER.png
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Xilinx Employee
Xilinx Employee
463 Views
Registered: ‎05-14-2008

Is this a show-stop problem?

Looks like a warning. Fit completed successfully, didn't it?

-vivian

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453 Views
Registered: ‎06-26-2019

Yes, some other problem.

But its fine.

I have one more doudt 

We are designing a schematic in Xilinx ISE 14.7 Version. So, now we are facing an issue in our design. In our previous design there is a symbol called “BUFE” But, in Xilinx 14.7 there is no such a symbol.

 

So, can you please suggest alternating symbol for BUFE.

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Xilinx Employee
Xilinx Employee
433 Views
Registered: ‎05-14-2008

Are you targeting CPLD or any other device?

-vivian

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426 Views
Registered: ‎06-26-2019

Hi,

We are curently designing for Spartan 6 board.

 

Regards,

Mohammed Aboo Saleh

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Xilinx Employee
Xilinx Employee
399 Views
Registered: ‎05-14-2008

Spartan6 does not have BUFE component.

It has BUFG, BUFIO2, BUFPLL, BUFH.

Usually we use BUFG.

For details about clock resources, please refer to UG382.

-vivian

 

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390 Views
Registered: ‎06-26-2019

Hi,

BUFE Means buffer with enable it is also active High enable.

BUFG is a simple buffer.

So, can any other symbol can replace exact BUFE operation.

 

Regards,

Mohammed Aboo Saleh

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Xilinx Employee
Xilinx Employee
383 Views
Registered: ‎05-14-2008

BUFG is actually one of the configurations of BUFGCTRL.

BUFGCTRL can be configured as BUFGCE.

I believe BUFGCE is what you need.

You can find the answer you need in UG382.

-vivian

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