07-03-2019 08:41 PM
07-03-2019 11:07 PM
Is this a show-stop problem?
Looks like a warning. Fit completed successfully, didn't it?
07-03-2019 11:17 PM
Yes, some other problem.
But its fine.
I have one more doudt
We are designing a schematic in Xilinx ISE 14.7 Version. So, now we are facing an issue in our design. In our previous design there is a symbol called “BUFE” But, in Xilinx 14.7 there is no such a symbol.
So, can you please suggest alternating symbol for BUFE.
07-04-2019 02:37 AM
Are you targeting CPLD or any other device?
07-04-2019 07:14 PM
Spartan6 does not have BUFE component.
It has BUFG, BUFIO2, BUFPLL, BUFH.
Usually we use BUFG.
For details about clock resources, please refer to UG382.
07-04-2019 08:16 PM
BUFE Means buffer with enable it is also active High enable.
BUFG is a simple buffer.
So, can any other symbol can replace exact BUFE operation.
Mohammed Aboo Saleh
07-04-2019 08:37 PM
BUFG is actually one of the configurations of BUFGCTRL.
BUFGCTRL can be configured as BUFGCE.
I believe BUFGCE is what you need.
You can find the answer you need in UG382.