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Observer larshb
Observer
433 Views
Registered: ‎08-30-2018

Timing closure through logic level retiming in synthesis

I am having some issues with timing closure for a design using the CAN-FD IP-core. I have noticed some of the issues are related to long critical paths due to high logic levels (example below). My question is; is there any way to do logic level retiming at synthesis time? (e.g. through XDC)

deleteme.png

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8 Replies
Xilinx Employee
Xilinx Employee
404 Views
Registered: ‎05-22-2018

Re: Timing closure through logic level retiming in synthesis

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Observer larshb
Observer
398 Views
Registered: ‎08-30-2018

Re: Timing closure through logic level retiming in synthesis

Thank you. I have already looked at that and the obvious solution is to improve the RLT (which I can not with the IP). The -retiming flag for synthesis only works for intra-clock paths. My corner cases are inter-clock paths for in-phase clocks that are x1 and x2 of the same frequency.

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Observer larshb
Observer
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Registered: ‎08-30-2018

Re: Timing closure through logic level retiming in synthesis

Update. I succeeded in using retiming on the core, however it cannot find ways to optimize the design. Any other suggestions for closure are welcome.

INFO: [Synth 8-5816] Retiming module `canfd_v2_0_0`
	Effective logic levels on critical path before retiming is: 11
	Total number of crtical paths = 330

	Optimizing at the module level
	Cannot find a feasible solution:
		Effective logic levels from inst/can_inst/CAN_PHY_RX_I_NEG_FLOP_X2_reg(fixed:INPUT) to inst/can_inst/tl/btl/CAN_PHY_TX_POS_FLOP_X2_reg(fixed:OUTPUT) is: 9
		Effective logic levels found across for latency (=1) is: 9
	Optimizing locally to improve critical paths(may not reduce worst delay)

	Effective logic levels on critical path after retiming is: 11
	Total number of crtical paths = 330
	Numbers of forward move = 0, and backward move = 0

bTADsSynthesized schematic

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Moderator
Moderator
358 Views
Registered: ‎03-16-2017

Re: Timing closure through logic level retiming in synthesis

Hi @larshb , 

Moving it to timing board since further suggestions required for timing closure. 

Regards,
hemangd

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Xilinx Employee
Xilinx Employee
338 Views
Registered: ‎05-14-2008

Re: Timing closure through logic level retiming in synthesis

This is a path from 80MHz clock domain to 160MHz clock domain.

What is the actual data toggle rate?

If the data actually toggles at 80MHz, you can use set_multicycle_path to relax the setup requirement of this path to 12.5ns, which means the destination clock captures the data every two cycles.

-vivian

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Observer larshb
Observer
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Registered: ‎08-30-2018

Re: Timing closure through logic level retiming in synthesis

Thanks Vivian. The actual toggle rate is hard for me to say as this is the CANFD IP-core and I cannot see the RTL. Nonetheless I've experimented with multi_cycle_path mostly resulting in "constraint explosion" (ie. relaxing one problematic path creates new ones).

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Xilinx Employee
Xilinx Employee
312 Views
Registered: ‎05-14-2008

Re: Timing closure through logic level retiming in synthesis

Too many logic levels and no retiming can be done by the tool, then in general you need to modify the code to reduce the logic levels, which is not possible in your case because this is an IP.

Based on the nature of this path (from 80MHz to 160MHz), this is a multi-cycle path as a 80MHz clock can only produces a signal toggling at 80MHz at most, and maybe even slower.

The IP should have gone with the multicycle path constraint itself if this is the case.

Please elaborate what new ones were brought in by your multicycle path constraint?

-vivian

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Historian
Historian
297 Views
Registered: ‎01-23-2009

Re: Timing closure through logic level retiming in synthesis

Based on the nature of this path (from 80MHz to 160MHz), this is a multi-cycle path as a 80MHz clock can only produces a signal toggling at 80MHz at most, and maybe even slower.

Be very careful with this line of thinking.

In order for a path to be multicycle, the source must not change for N consecutive cycles, and the destination must only capture the result at the end the Nth cycle - only then is it an N cycle multi-cycle path. So the fact that it is launched by an 80MHz clock only satisfies the first part of this requirement - we have no information about the second.

For the second to be true:

  • There must be logic on the 160MHz domain that determines the phase of the 80MHz clock
    • i.e. which 160MHz clock corresponds to the first cycle after the rising edge of the 80MHz clock and which corresponds to the second
  • The flip-flops capturing the data on the 160MHz domain are only enabled on the 2nd clock

Without this, this path is not multi-cycle in the 160MHz domain. Therefore declaring it multi-cycle would be an error; this will result in the desing passing timing, but will create a system that can (and likely will) fail in the real world.

Avrum