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1,054 Views
Registered: ‎03-03-2017

Timing closure training option?

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Hi,

   I am finding I am spending 50 to 75% of my time lately trying to get timing to pass in the designs I am working with at work.   I was wondering if anybody had a recommendation for training to help with timing closure techniques.   

Thanks 

Tim

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Moderator
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1,396 Views
Registered: ‎09-15-2016

Re: Timing closure training option?

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Hi @tim_severance

 

Did you check the below docs? They are specifically meant for timing closure guidelines.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug949-vivado-design-methodology.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug906-vivado-design-analysis.pdf

 

Regards

Rohit

Regards
Rohit
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Moderator
Moderator
1,397 Views
Registered: ‎09-15-2016

Re: Timing closure training option?

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Hi @tim_severance

 

Did you check the below docs? They are specifically meant for timing closure guidelines.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug949-vivado-design-methodology.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug906-vivado-design-analysis.pdf

 

Regards

Rohit

Regards
Rohit
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Moderator
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Registered: ‎01-16-2013

Re: Timing closure training option?

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Hi,

I hope the training provided by the thakur is good.

Apart from topic, always check constraints coverage (I hope you are using Vivado) in Vivado all clocks are consider as synchronous unless specified.

Also check if the clocking topology you are using is as per architecture and follow methodology in UG949.

Check if there is any scope of RTL optimization.

This all techniques will help to reduce your effort at timing closure.

Thanks,
Yash
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Observer
Observer
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Registered: ‎08-17-2016

Re: Timing closure training option?

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I would like to suggest looking at InTime - https://www.plunify.com/en/intime/ (Disclosure: I work for Plunify) It is a software that derives the best/optimum compilation settings necessary to close or optimize timing, without changing RTL. It is not a substitute for good design practices or architectures. However, it helps in cases where you are hand tied and can't change the RTL (e.g. a 3rd party IP core). Or you are trying to crank out the last X% performance from your design. Based on our experience, with the right knobs, the Vivado software becomes a very powerful compilation tool. We have seen it solve massive routing congestion issues, WNS of -2 to -3ns of worst slack down to less than 10ps. 

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InTime - Timing Optimization with ML (Blog)
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