You should consider the two data transfers as completely separate events.
Firstly, you will need an OFFSET = IN constraint for the ADC-FPGA data. This is a source-synchronous interface using CLK1 (I hope that CLK1 is connected to a global clock pin).
Secondly, you will need an OFFSET = OUT constraint for the FPGA-DAC data. This is a source system-synchronous interface as CLK2 is the input clock used to drive the outputs to the DAC (I hope that CLK2 is connected to a global clock pin).
There is no "magic" timing constraint that will make your design work. As you have, effectively, an asynchronous data transfer (i.e. there is no definable relationship between CLK1 and CLK2), I believe you are completely correct to use a two-clock FIFO to handle the passage of data through the FPGA.
---------- "That which we must learn to do, we learn by doing." - Aristotle