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amin_8460
Visitor
Visitor
5,241 Views
Registered: ‎11-27-2012

Timing constraint digital loop back by DAC ADC

Hi

I intend to make a digital loop back from ADC to DAC. I mean send whatever is being received from ADC to DAC.

both clocks are same at frequency but they have different phase. Worse, their phase coulde changed in evey power up.

Is there any timing constraint to ensure the set up and hod time will be met?

I already used a FIFO to solve my problem without using any constraint. that works but I think there is a better solution.

 

I have depicted the situaton:

 

ADCDAC.JPG

 

Thanks,

Amin

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hgleamon1
Teacher
Teacher
5,229 Views
Registered: ‎11-14-2011

You should consider the two data transfers as completely separate events.

 

Firstly, you will need an OFFSET = IN constraint for the ADC-FPGA data. This is a source-synchronous interface using CLK1 (I hope that CLK1 is connected to a global clock pin).

 

Secondly, you will need an OFFSET = OUT constraint for the FPGA-DAC data. This is a source system-synchronous interface as CLK2 is the input clock used to drive the outputs to the DAC (I hope that CLK2 is connected to a global clock pin).

 

There is no "magic" timing constraint that will make your design work. As you have, effectively, an asynchronous data transfer (i.e. there is no definable relationship between CLK1 and CLK2), I believe you are completely correct to use a two-clock FIFO to handle the passage of data through the FPGA.

 

Regards,

 

Howard

 

 

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"That which we must learn to do, we learn by doing." - Aristotle