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Visitor csk206x
Visitor
5,480 Views
Registered: ‎08-01-2011

Timing constraint error when increase the spartan-6 Microblaze clock freq to 200Mhz

 

Hi,

I am using Spartan-6 FPGA SP605 evaluation Kit and trying to increase the spartan-6 to 200 Mhz, however ISE tool updating the timing model, It encountered error:pack:1653

ERROR:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.

 

One thing that I notice is when creating the system using BSB, the clock wizard only allow to configure the max microblaze clock freq to 90Mhz. Is this the limitation of the spartan-6 board that i am using? Only able to configure the microblaze frequency to 200Mhz after I checked the box for Enable full dynamic range of clock frequencies (allow 1Mhz to 1000Mhz for spartan6-3 )

 

 

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4 Replies
Xilinx Employee
Xilinx Employee
5,477 Views
Registered: ‎01-03-2008

Re: Timing constraint error when increase the spartan-6 Microblaze clock freq to 200Mhz

This error message means that even if the route delays were zero the timing constraint of 200 MHz cannot be met.
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Explorer
Explorer
5,472 Views
Registered: ‎08-14-2007

Re: Timing constraint error when increase the spartan-6 Microblaze clock freq to 200Mhz

Just because you can request a clock frequency doesn't mean that the logic you are trying to put in the FPGA will run at that frequency.

 

Microblaze is a great bit of engineering, but getting it to run at 200MHz in S6 is asking a little too much.

 

 

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
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Historian
Historian
5,466 Views
Registered: ‎02-25-2008

Re: Timing constraint error when increase the spartan-6 Microblaze clock freq to 200Mhz


@csk206x wrote:

 

Hi,

 

I am using Spartan-6 FPGA SP605 evaluation Kit and trying to increase the spartan-6 to 200 Mhz, however ISE tool updating the timing model, It encountered error:pack:1653

 

ERROR:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.

 

One thing that I notice is when creating the system using BSB, the clock wizard only allow to configure the max microblaze clock freq to 90Mhz. Is this the limitation of the spartan-6 board that i am using? Only able to configure the microblaze frequency to 200Mhz after I checked the box for Enable full dynamic range of clock frequencies (allow 1Mhz to 1000Mhz for spartan6-3 )

 

 


It sounds like the tools know the maximum clock frequency attainable for MicroBlaze in the particular FPGA and speed grade in question. (This is not a function of the board, it's a function of the chosen FPGA device.) Since the tools know that the MicroBlaze won't go much faster than 90 MHz in that chip, they won't let you select a higher clock frequency.

 

When you tried to target 200 MHz, the tools told you that the logic itself for some paths (doesn't matter what they are) in the MicroBlaze design cannot go that fast, hence the errors.

----------------------------Yes, I do this for a living.
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Visitor csk206x
Visitor
5,455 Views
Registered: ‎08-01-2011

Re: Timing constraint error when increase the spartan-6 Microblaze clock freq to 200Mhz

 

Okay. It sound like the limit of the Spartan-6 chip that i am using.

Besides using the BSB tool, is there any document specify the max speed limit of Spartan-6 microblaze can be running?

Thanks 

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