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Adventurer
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Registered: ‎01-02-2008

Timing constraint - set input delay (again) for synchronous circuit with external combinatorial logic

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Hello,

I can't seem to find the answer anywhere else. 

How to set input delay for a circuit that has the launch Flop inside FPGA, going out to another chip, enabling data buffer, then data is latched by a flip inside the FPGA. Those flops are on the same clk, inside FPGA.

FLOPA --> FPGA-PINA --> External Chip Output enable --> FPGA-PINB --> FLOPB

I know the PAD-To-PAD delay of the external chip, how can i set input delay for the FPGA_PINB? and How can i view the report?

The reference pin parameter doesn't seem to work.

Thanks guys,

Regards, 

Jeff

 

 

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Guide
Guide
6,713 Views
Registered: ‎01-23-2009

Re: Timing constraint - set input delay (again) for synchronous circuit with external combinatorial logic

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So, first, it is rarely correct to use a set_max_delay on an output - it is always better to use a set_output_delay.

 

Furthermore, the mechanism you have shown only constrains the maximum, not the minimum.

 

Also, you are making an arbitrary allocation of time for the output and time for the return path...

 

I think all of this can be fixed using a generated clock. I know the outputs are not "clocks" but are strobes, but from the timing point of view, I don't think this matters.

 

Using your notation, you would create the generated clock on the output port

 

create_generated_clock -name MY_STROBE -divide_by 1 -source [get_pins FLOPA/C] [get_ports FPGA_PINA]

 

Then you would set the input delay for the input, which would be the sum of the board delay to the device, the propagation delay through the device and the board delay back to the FPGA. You would do the calculation twice - once for the max of all these delays and once for the min.

 

set_input_delay -clock MY_STROBE <max_calculated_above> [get_ports FPGA_PINB]

set_input_delay -clock MY_STROBE -min <min_calculated_above> [get_ports FPGA_PINB]

 

If you have two pins acting as strobes (say the RD and OE) then you can do this twice.

 

Create a second generated clock (MY_STROBE2) on the second output port and a second set of input delays, but use the -add_delay option so that the second ones don't override the first

 

set_input_delay -clock MY_STROBE2 -max <max_of_2nd_path> [get_ports FPGA_PINB] -add_delay

set_input_delay -clock MY_STROBE2 -min <min_of_2nd_path> [get_ports FPGA_PINB] -add_delay

 

It probably is worth mentioning that all the FFs involved here should be placed in the IOB (use the IOB property on all the ports involved).

 

Try this out and let us know if it works...

 

Avrum

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Guide
Guide
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Registered: ‎01-23-2009

Re: Timing constraint - set input delay (again) for synchronous circuit with external combinatorial logic

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You don't tell us what tool you are using - ISE or Vivado.

 

If it is ISE, then you can't - the timing engine and constraint mechanism just aren't powerful enough. Take a look at this post on a similar question - basically you have to do this all manually.

 

Avrum

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Adventurer
Adventurer
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Registered: ‎01-02-2008

Re: Timing constraint - set input delay (again) for synchronous circuit with external combinatorial logic

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Thank you. 

I forgot to mention I'm using Vivado timing tool. 

I managed to do it this way manually, but I'm not sure I got it correctly. 

 

#Constraint the clock to output on FPGA PINA to maximum of 6 ns.

set_max_delay -datapath_only -from [get_pins FLOPA/C] -to [get_ports FPGA_PINA] 6.0

 

#Use that maximum delay of 6ns to constraint the input using the same clock.

set_input_delay -clock [FLOP_B's Clock] -max [6.0 + (External Logic Delay)] [get_ports FPGA_PINB]

 

The timing report seems to make sense. 

 

But I wonder what's the right way to do it. 

 

Thank you for replying

Regards,

Jeff

 

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Guide
Guide
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Registered: ‎01-23-2009

Re: Timing constraint - set input delay (again) for synchronous circuit with external combinatorial logic

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So, first, it is rarely correct to use a set_max_delay on an output - it is always better to use a set_output_delay.

 

Furthermore, the mechanism you have shown only constrains the maximum, not the minimum.

 

Also, you are making an arbitrary allocation of time for the output and time for the return path...

 

I think all of this can be fixed using a generated clock. I know the outputs are not "clocks" but are strobes, but from the timing point of view, I don't think this matters.

 

Using your notation, you would create the generated clock on the output port

 

create_generated_clock -name MY_STROBE -divide_by 1 -source [get_pins FLOPA/C] [get_ports FPGA_PINA]

 

Then you would set the input delay for the input, which would be the sum of the board delay to the device, the propagation delay through the device and the board delay back to the FPGA. You would do the calculation twice - once for the max of all these delays and once for the min.

 

set_input_delay -clock MY_STROBE <max_calculated_above> [get_ports FPGA_PINB]

set_input_delay -clock MY_STROBE -min <min_calculated_above> [get_ports FPGA_PINB]

 

If you have two pins acting as strobes (say the RD and OE) then you can do this twice.

 

Create a second generated clock (MY_STROBE2) on the second output port and a second set of input delays, but use the -add_delay option so that the second ones don't override the first

 

set_input_delay -clock MY_STROBE2 -max <max_of_2nd_path> [get_ports FPGA_PINB] -add_delay

set_input_delay -clock MY_STROBE2 -min <min_of_2nd_path> [get_ports FPGA_PINB] -add_delay

 

It probably is worth mentioning that all the FFs involved here should be placed in the IOB (use the IOB property on all the ports involved).

 

Try this out and let us know if it works...

 

Avrum

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Adventurer
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Re: Timing constraint - set input delay (again) for synchronous circuit with external combinatorial logic

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Hi 

Yeah this works. It has the advantage of constraining both min/max, seems to be the better choice.

I tried that. 

 

Just to advance the discussion further. For my particular case, I do have a real clock send to the device. And I actually have created that output clock. 

 

create_generated_clock -name outclk ... [get_ports outclk_port]

 

The small problem is I do have a legitimate path from FPGA_PINA to the device, as source synchronous kind of system.

 

And I also need a

 

set_output_delay -clock outclk -reference_pin outclk_port -max/min [get_port FPGA_PINA]. 

 

So when I tried your method of making a fake clock on FPGA_PINA:

- The tool DOES report the correct path from FPGA_PINA to FPGA_PINB 

- But the tool also gives a weird path from the "fake clock" MY_STROBE to the actual clock outclk, because of my output_delay constraint above.

 

Making a false path between the clocks solved the problem. 

 

Thank you very much!!!

Now, I'm confident that there's no straight way to constrain this type. 

Create a "fake" clock would do the trick. 

 

Best regards, 

Jeff

 

p.s I thought that using reference_pin to point to the FPGA_PINA, alone could do it, but apparently the tool doesn't do anything: 

 

set_input_delay -clock FLOP_B_CLOCK -reference_pin FPGA_PINA -max/min ... [get_ports FPGA_PINB]