UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer floorbalint
Observer
391 Views
Registered: ‎07-31-2017

Timing constraints, MMCM from tcl

Jump to solution

Hello,

I'm working on a project, wich contains a lot of IP core. I would like to leave the project mode developeing, and make the whole project generated from tcl scripts, and I've got some issue with de clock generation. In the original project I use a clocking_wizard IP core, which generates an MMCM. I've would like to keep this structure.

 

I can generate the IP cores from tcl scripts expect the clocking wizard. I cant find the parameters to this object, which can be manipulated from the tcl scripts. I tried to solve this clocking problem only from the constraint files, but when I use the create_clock or create_generated_clock commands, vivado always eliminate the MMCM objects from the project.

 

So the question is: how can I make the same clocking structure, as the clocking wizard does, but without any IP core generator, only use tcl scripts?

 

Balint

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Historian
Historian
284 Views
Registered: ‎01-23-2009

Re: Timing constraints, MMCM from tcl

Jump to solution

So there are a couple of answers/considerations here.

But first...

I would like to leave the project mode developeing, and make the whole project generated from tcl scripts

We need to be careful here.. There are two modes of Vivado - "Project mode" and "Non-project mode" (previously and confusingly called "Non-project batch mode"). Then there are two ways of interacting with the too - through the GUI and through Tcl scripts. These are not the same thing - these describe four separate situations, all of which are valid (and most of which are useful). Of particular note is that you can use "fully scripted" and "Project mode" together. So, to be clear, just because you want to use Tcl scripts does not mean you are "leaving project mode developing".

Next, there are many ways of dealing with MMCMs in a design. In some ways, the simplest approach (if you don't want to get involved in all kinds of complex flow stuff) is simply to instantiate the MMCM in your RTL; the MMCM is a cell and can be instantiated like any other primitive, including setting all the attributes of the MMCM in the RTL. The Language Templates (Tools -> Language Templates) give you examples (i.e. Verilog -> Device Primitive Instantiation -> <Device> -> Clock Components -> MMCM/PLL) give you templates of how to do this.

Also, (and I don't recommend this for any IP other than the clocking wizard), one of the output products of the clocking wizard is synthesizable RTL code - you can generate the clocking wizard core (in a separate project) and then copy the generated code into your RTL design - it can be found in the Sources -> IP Sources -> IP -> <core name> -> Synthesis -> <core_name>_clk_wiz.v file.

Finally, you can fully automate the IP creation process using Tcl scripts - using something like this

    create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name clk_core
    set_property -name CONFIG.PRIM_IN_FREQ -value $freq_in_num -objects [get_ips clk_core]
    set_property -name CONFIG.CLKOUT2_USED -value {true} -objects [get_ips clk_core]
    set_property -name CONFIG.CLKOUT1_REQUESTED_OUT_FREQ -value $freq_rx_num -objects [get_ips clk_core]
    set_property -name CONFIG.Clkout2_REQUESTED_OUT_FREQ -value $freq_tx_num -objects [get_ips clk_core]
    set_property -name CONFIG.PRIM_SOURCE -value {Differential_clock_capable_pin} -objects [get_ips clk_core]
    generate_target  {instantiation_template synthesis}  [get_files clk_core.xci] -force

The actual configuration, though, will depend on your use case. The easiest way to get this done right is to (again) create the core in a separate project. When you do so, the Tcl window will contain the set of Tcl commands (that look like the ones above) required to generate the core. You can copy them from the Tcl window (or the Tcl log) and place them in your script (after modifying them accordingly).

Avrum

1 Reply
Highlighted
Historian
Historian
285 Views
Registered: ‎01-23-2009

Re: Timing constraints, MMCM from tcl

Jump to solution

So there are a couple of answers/considerations here.

But first...

I would like to leave the project mode developeing, and make the whole project generated from tcl scripts

We need to be careful here.. There are two modes of Vivado - "Project mode" and "Non-project mode" (previously and confusingly called "Non-project batch mode"). Then there are two ways of interacting with the too - through the GUI and through Tcl scripts. These are not the same thing - these describe four separate situations, all of which are valid (and most of which are useful). Of particular note is that you can use "fully scripted" and "Project mode" together. So, to be clear, just because you want to use Tcl scripts does not mean you are "leaving project mode developing".

Next, there are many ways of dealing with MMCMs in a design. In some ways, the simplest approach (if you don't want to get involved in all kinds of complex flow stuff) is simply to instantiate the MMCM in your RTL; the MMCM is a cell and can be instantiated like any other primitive, including setting all the attributes of the MMCM in the RTL. The Language Templates (Tools -> Language Templates) give you examples (i.e. Verilog -> Device Primitive Instantiation -> <Device> -> Clock Components -> MMCM/PLL) give you templates of how to do this.

Also, (and I don't recommend this for any IP other than the clocking wizard), one of the output products of the clocking wizard is synthesizable RTL code - you can generate the clocking wizard core (in a separate project) and then copy the generated code into your RTL design - it can be found in the Sources -> IP Sources -> IP -> <core name> -> Synthesis -> <core_name>_clk_wiz.v file.

Finally, you can fully automate the IP creation process using Tcl scripts - using something like this

    create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name clk_core
    set_property -name CONFIG.PRIM_IN_FREQ -value $freq_in_num -objects [get_ips clk_core]
    set_property -name CONFIG.CLKOUT2_USED -value {true} -objects [get_ips clk_core]
    set_property -name CONFIG.CLKOUT1_REQUESTED_OUT_FREQ -value $freq_rx_num -objects [get_ips clk_core]
    set_property -name CONFIG.Clkout2_REQUESTED_OUT_FREQ -value $freq_tx_num -objects [get_ips clk_core]
    set_property -name CONFIG.PRIM_SOURCE -value {Differential_clock_capable_pin} -objects [get_ips clk_core]
    generate_target  {instantiation_template synthesis}  [get_files clk_core.xci] -force

The actual configuration, though, will depend on your use case. The easiest way to get this done right is to (again) create the core in a separate project. When you do so, the Tcl window will contain the set of Tcl commands (that look like the ones above) required to generate the core. You can copy them from the Tcl window (or the Tcl log) and place them in your script (after modifying them accordingly).

Avrum