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Visitor spthomps
Visitor
304 Views
Registered: ‎09-18-2018

Timing constraints and Fmax for soft-core processor

Hello,

I'm working on evaluating a SiFive E31 RISC-V soft-core on the Artix A7 dev board. I'm currently working to find out what the Fmax is of the processor is, and whether my timing reports are giving me factual errors, or if my constraints are not correct. The design is very simple: a PLL, and the processor.


The PLL creates three clocks:

     1. Core Clock (325MHz)
     2. Peripheral Clock (325MHz)
     3. RTC Clock (8.388 MHz)


These three clocks are used as separate inputs to the core. When I run implementation, I get very large amounts of Total Negative Slack ranging from (-1000 to -100000) depending on what I have the Core and Peripheral clocks set to. Am I right in my assumption that if this TNS is > 0, the core most likely will not work 100% as expected? What are the steps to take to hopefully fix these input clock errors to the core?

Screenshot from 2019-07-15 14-06-32.png


With this being said, I'm also curious on how to calculate the Fmax of the soft-core processor. With Vivado they seem to focus more on slack, so would I take the worst-case register pair in the design (highest slack) and calculate my Fmax from that?

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7 Replies
Xilinx Employee
Xilinx Employee
268 Views
Registered: ‎05-14-2008

Re: Timing constraints and Fmax for soft-core processor

Please refer to below AR:

https://www.xilinx.com/support/answers/57304.html

Hope it helps.

-vivian

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Scholar dpaul24
Scholar
259 Views
Registered: ‎08-07-2014

Re: Timing constraints and Fmax for soft-core processor

@spthomps,

Have you exclusively mentioned in the timing constraints file that all those clocks are unrelated (I hope they are so by design)?

Vivado will assume by default that all clocks are related and so can produce huge violations.

Better to put your constraints file here so that we can see what is done.

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Visitor spthomps
Visitor
226 Views
Registered: ‎09-18-2018

Re: Timing constraints and Fmax for soft-core processor

Hey @dpaul24 ,

Sorry, I totally forgot to include my constraints file! It's now attached, but it's rather short.

I've used the "set_clock_groups -async" constraint to say all of the PLL clocks are unrelated:

create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clock}];
create_clock -add -name jtag_clk -period 100 -waveform {0 50} [get_ports {jtag_tck}];

set_clock_groups -async -group [get_clocks core_clock_clk_wiz_0]
set_clock_groups -async -group [get_clocks peripheral_clock_clk_wiz_0]
set_clock_groups -async -group [get_clocks rtc_clock_clk_wiz_0]
set_clock_groups -async -group [get_clocks sys_clk_pin]
set_clock_groups -async -group [get_clocks jtag_clk]

This fixed my initial issue of the "inter-clock" path violations. The issue now is with the "intra-clock" path violations.

Screenshot from 2019-07-16 09-33-26.png

Unfortunately, the core is obfuscated so I'm not sure what the path in the "To" column is actually going towards, but this seems to be the core_clock_clk_wiz_0 to the CLKBWRCLK in the data_arrays_0_0_ext/ram_reg_3/ object?

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Xilinx Employee
Xilinx Employee
166 Views
Registered: ‎05-14-2008

Re: Timing constraints and Fmax for soft-core processor

Looks like those failing paths are from Block RAM to registers' clock enable pins.

There are 12 logic levels and 80 fanout.

I suggest you add a pipeline register at the Block RAM output, and add another register to drive the 80 clock enable pins of the registers.

In this way you may be able to resolve the high logic levels and high fanout.

-vivian

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Xilinx Employee
Xilinx Employee
164 Views
Registered: ‎05-14-2008

Re: Timing constraints and Fmax for soft-core processor

And this summary report does not give enough info to analyze the failing paths.

It'll be better to provide the detailed path analysis.

When you click on any row in this summary table, the detailed analysis of this path will be open in the main window.

-vivian

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Visitor spthomps
Visitor
140 Views
Registered: ‎09-18-2018

Re: Timing constraints and Fmax for soft-core processor

@viviany 

Thank you for the information. Is there a preferred way to provide the whole report of one of the violations? It seems Vivado opens up four separate windows that I can export to a spreadsheet.

Also, one thing to note is that this is a provided soft-core professor for a trial. Can I conclude that this is not something to do with my integration of the core, and that there is something wrong with their design?

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Xilinx Employee
Xilinx Employee
121 Views
Registered: ‎05-14-2008

Re: Timing constraints and Fmax for soft-core processor

The text timing report is in the <project_name>.runs/impl_x folder with name xxxx_routed_timing_summary.rpt.

If the startpoints and endpoints are all within the soft core, yes, it is the core not meeing the 100MHz clock freuquency.

-vivian

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