05-26-2019 02:30 PM - edited 05-26-2019 02:34 PM
I am learning FPGA design. I have small design with 2 RAM instances of RAM IP generated modules, a multiplier and some LEDs, Switches in circuit.
After synthesis & implementation, I try to create a new constraints file with custom IO planning and timing constraints. I can successfully place IO Ports Pin maps, but when it comes to timing maps, when I add a set_maximum_delay constraint, the constraint editor creates multiple duplicates after re-running implementation with new constraint file. Any suggestions would be greatly appreciated. Thank you.
Vivado Version: 2018.2 (SW build 2258646)
05-26-2019 11:27 PM
Would you please elaborate on "the constraint editor creates multiple duplicates"?
05-27-2019 09:19 AM
05-28-2019 12:05 AM
If you add set_max_delay constraint via Constraint Editor, it's saved in memory and not written to target XDC until you save the design. Do you mean you observe multiple lines of the same set_max_delay constraint after you save to XDC?