UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor richnsim
Visitor
869 Views

Timing constraints for a gated clock output

Jump to solution

Hello

 

I want to interface an ADC with a Zync UltraScalte+ SoC. I need to supply a clock signal to the ADC to read its data over a simple SPI-like interface. However the clock should be quiet during data conversion and only be enabled after conversion for exactly 20 clock cycles.

 

When I use the following code, it works fine, but I’m a bit worried about the relation between my clock enable and the clock itself. As the enable signal is latched on the positive edge, I’m afraid the delay between my clock enable register and the clock buffer might cause a glitch on my output clock:

 

clk_out <= pll_clk WHEN clk_en = '1' ELSE '0';

gated_clock

 

gated_clock_implementation

 

I’m afraid of the following scenario:

 

Clock_Enable3.jpg

 

Are these baseless worries, i.e. does Vivado handle the situation on its own, or is there any way to set a timing constraint to make sure this will work under any circumstance?

 

Best Regards

Simon

 

 

PS: I know there are different ways of implementing this, but for general knowledge, I would like to know if/how it can be done with a gated clock.

1 Solution

Accepted Solutions
1,030 Views

Re: Timing constraints for a gated clock output

Jump to solution

@richnsim

 

UG572 describes clocking resource for the Zynq Ultrascale+.  Page 29 says that the BUFGCE “provides glitchless clock gating”.

 

As drjohnsmith says, clock buffers like the BUFGCE are designed to output into the FPGA clock tree which can then drive the clock pin of any device in the FPGA.  For the 7-Series FPGAs, UG472 had a nice table (Table 1-1) showing valid inputs and outputs for all the clock buffers. Unfortunately, I don’t see a similar table in UG572.  However, I'm fairly sure that for your FPGA, the clock-pin/OBUF is not a valid output for the BUFGCE.

 

I also agree with drjohnsmith’s recommendation to use the ODDR primitive (UG571, pg159) as a valid way to remove a clock from the clock tree – and send it to an FPGA pin.  It is a valid way because the output of your BUFGCE drives the click pin of the ODDR as shown in the following image which is from page 30 of UG903.

ODDR_fwd_clock.jpg

 

Mark

11 Replies
Scholar jmcclusk
Scholar
850 Views

Re: Timing constraints for a gated clock output

Jump to solution

The canonical method for generating a gated clock is to use the BUFGCE element, which is guaranteed not to generate glitches by design.  Using a LUT for clock gating is the canonical method for generating glitches.

Don't forget to close a thread when possible by accepting a post as a solution.
831 Views

Re: Timing constraints for a gated clock output

Jump to solution

Hi @richnsim

 

I agree with warning from jmcclusk about the LUT in your schematic.  Whether you are sending a clock or a signal out of the FPGA, you should never drive the FPGA pin with a LUT since this can send glitch pulses out of the FPGA.  Currently you have (FDRE > LUT2 > OBUF > CLK_OUT).  The recommendation is to rewrite your VHDL so that you have (FDRE > LUT2 > FDRE > OBUF > CLK_OUT).

 

However, before you do that, we need to talk a little about the SPI interface…

 

Serial interfaces like SPI and I2C usually run at slow clock speeds (typ < 1MHz).   For these slow interfaces, the clock, SCK, is usually not generated by a Clock Management Tile (ie. MMCM or PLL).  Instead, SCK and data, MOSI/MISO, are simply signals that you toggle with your VHDL code.  The clock gating you are trying to implement in hardware is also done using VHDL.  Further, you toggle clock and data lines in such a way that the SPI interface is said to pass timing analysis “by design”. That is, constraints and formal timing analysis are not needed.

 

Here’s an example that will explain this “all VHDL” SPI interface.  Let’s assume that you are the SPI master (ie. you control SCK) and SCK is being toggled at 0.5MHz.  First, you use the PLL to generate a fast pacer clock, CLKP, which will toggle at 10MHz for this example.  Next, find a timing diagram for your SPI interface.  We’ll use the following diagram that I got from <here>.
SPI_Timing.jpg

 

Since SCK=0.5MHz, we’ll assume that TCH=TCL=1us. We’ll also assume TLS1=1us.  For SPI communications, note that the data lines (MOSI and MISO) change slightly after the falling edge of SCK.  As with most communication interfaces, you want to read the data line in the middle of the “data eye”, which coincides with the rising edge of SCK for SPI.  So, you write your VHDL code (typically using a state machine) to do the following (for a SPI Master):

  1. Ensure SPI interface is in the idle state: CSB=1, SCK=0
  2. Wait for a trigger from other parts of your VHDL to start communication (this is the clock gating you wanted).
  3. Set CSB=0 and place the first data bit on MOSI
  4. Wait 1us (ie. count 10 cycles of CLKP) for TLS1
  5. Set SCK=1 and read the data bit from MISO (here you have read the data in the middle of the data eye which means you are passing timing analysis by design).
  6. Wait 1us (ie. count 10 cycles of CLKP) for TCH
  7. Set SCL=0 and place the next data bit on MOSI
  8. Wait 1us (ie. count 10 cycles of CLKP) for TCL
  9. Set SCK=1 and read the next data bit from MISO
  10. … and so on until all data bits have been sent/received and then return to 1)

You will find VHDL code that implements SPI <here>.  I have not tested this code but it looks well written and documented.

 

Good luck!

Mark

 

PS. Avrum will tell you to put those final registers (the one that directly drive or receive data from the FPGA pins) into the IOB.

 

0 Kudos
Visitor richnsim
Visitor
812 Views

Re: Timing constraints for a gated clock output

Jump to solution

Dear markg@prosensing.com

 

Thanks for your input. I don’t want to be rude, but I explicitly wrote I don't want any "none gated clock" solutions! Apart from that you may want to review your idea of SPI: Many modern ADCs have SPI interfaces that run at up to 100MHz like the LTC2378-20 I’m using.

 

I don’t want to go into much further details, but in my special case I use the ADC in combination with a digital isolator that has some signal distortion, to compensate for this I use a 85MHz clock with a 60% duty-cycle. To achieve this by just “toggling some signals” as you suggested, I would need a clock running at 850MHz which is not very realistic!

 

Best Regards

Simon

 

 

 

0 Kudos
Scholar drjohnsmith
Scholar
806 Views

Re: Timing constraints for a gated clock output

Jump to solution

You will get a glitch if you use a LUT to gate a clock.

 

not always, not on every build of the code,

    but it will happen and you will be caught out.

 

don't do it,

 

 

You mention about distortion on the clock line due to the isolator,

   Im interested, I did a design a while back, similar, 

       but the duty cycle of the shift out clock did not have to be 50:50 

             Wondering why your concerned .

 

Good luck, 

    getting even 18 bits was fun, 

          even flux left under a ball on a chip at 20 bits makes more noise that the LSB....

 

 

0 Kudos
Visitor richnsim
Visitor
804 Views

Re: Timing constraints for a gated clock output

Jump to solution

Dear @jmcclusk

 

Thanks for your input. I'm an Altera user and freshly starting with Xilinx. To me it is very uncommon to instantiate primitives in my own code. I have read an answer from avrumw on a different post that suggested using a BUFGCE for gated clocks as well.

 

Maybe I did something wrong, but when I used a BUFGCE in my design, that is when the glitches started! I will give it another try today, but anyways, you stated that a BUFGCE “is guaranteed not to generate glitches by design”. This brings me back to the core of my question:

When using a BUFGCE you say, I don’t need to set any timing constraints at all to avoid glitches - is that correct?

0 Kudos
Visitor richnsim
Visitor
792 Views

Re: Timing constraints for a gated clock output

Jump to solution

Here is the picture of the implementation using a BUFGCE:

gated clock with BUFGCE

 

The only primitive instantiated by me is the BUFGCE marked with a blue star before the OBUF:

 

BUFGCE_inst : BUFGCE
   generic map (
      CE_TYPE => "SYNC", -- ASYNC, SYNC
      IS_CE_INVERTED => '0', -- Programmable inversion on CE
      IS_I_INVERTED => '0' -- Programmable inversion on I
   )
   port map (
      O => CLK_OUT, -- 1-bit output: Buffer
      CE => clk_en, -- 1-bit input: Buffer enable
      I => pll_clk -- 1-bit input: Buffer
   );

I copied this code from the Xilinx UG974. Can you please tell me, what the CE_TYPE => “SYNC” generic does?

 

This implementation basically ANDs my clock enable with the global clock enable of the pll clock buffer and uses it on the un-buffered clock signal from the pll. This is not quite what I would have expected, but it matches the answer from avrumw given in a post I mentioned earlier.

 

What makes me feel positive about this solution is, that Vivado now recognizes a timing path to the BUFGCE which was not the case in my first attempt with only the LUT. 

 

 

Still my question remains: Is this safe now (without any constraint)?

0 Kudos
Scholar drjohnsmith
Scholar
781 Views

Re: Timing constraints for a gated clock output

Jump to solution

I also jump between Altera / Intel , Xilinx and Latice worlds,

    all are the same but different as you have seen.

 

 

If its of use, I can pass on what I did for the 18 bit adc.

 

Dont gate a clock as such

 

I controlled the signals from a state machine,

       The 'trick' is to the the DDR IOB in the device.

 

This can be enabled by a single bit into it,

   and feed a single clock at the frequency you want 

 

The gated clock buffers in Xilinx are normally used for internal clocks ,

 

I can't remember what chip your using ( sorry phone is not good at big screens )

 

Have a look here 

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

page 126 area, 

 

Use same_edge mode.

   Set input D1 as '0'

     If input D2 is '0', then no clock out, if input D2 is '1', then clock out.

 

No glitch, fully synchronous to the internal clock 

    

 

 

1,031 Views

Re: Timing constraints for a gated clock output

Jump to solution

@richnsim

 

UG572 describes clocking resource for the Zynq Ultrascale+.  Page 29 says that the BUFGCE “provides glitchless clock gating”.

 

As drjohnsmith says, clock buffers like the BUFGCE are designed to output into the FPGA clock tree which can then drive the clock pin of any device in the FPGA.  For the 7-Series FPGAs, UG472 had a nice table (Table 1-1) showing valid inputs and outputs for all the clock buffers. Unfortunately, I don’t see a similar table in UG572.  However, I'm fairly sure that for your FPGA, the clock-pin/OBUF is not a valid output for the BUFGCE.

 

I also agree with drjohnsmith’s recommendation to use the ODDR primitive (UG571, pg159) as a valid way to remove a clock from the clock tree – and send it to an FPGA pin.  It is a valid way because the output of your BUFGCE drives the click pin of the ODDR as shown in the following image which is from page 30 of UG903.

ODDR_fwd_clock.jpg

 

Mark

749 Views

Re: Timing constraints for a gated clock output

Jump to solution

markg@prosensing.com

 

And if I may butt in, another approach that may reduce the chance of a glitch is to use either the D1 or D2 ODDR inputs from your diagram as a clock output enable.  The clock must then stop on either a rising or falling edge, depending on which input you choose.

Visitor richnsim
Visitor
297 Views

Re: Timing constraints for a gated clock output

Jump to solution

Hi guys

 

Thank you all very much for your inputs!

 

To summarize the topic:

There are two ways to create a safe (glitch-free) gated output clock signal:

 

1. Using a ODDR (preferred way)

As @drjohnsmith mentioned, by setting one input to ‘0’, the other input can be used as a synchronous enable for the clock signal. The same was basically suggested by avrumw here.

 

2. Using a BUFGCE

As @jmcclusk pointed out first, a BUFGCE will guarantee a glitch-free clock signal. But I agree with drjohnsmith, that a BUFGCE is rather supposed to be used for internal clocks.

 

I both cases the timing of the clock enable is monitored internally, therefore no explicit timing constraints are needed.

 

I marked markg@prosensing.com's answer as solution, because it mentions both ways and has a lot of references to helpful user guides.

 

Best Regards

Simon

278 Views

Re: Timing constraints for a gated clock output

Jump to solution

@richnsim

 

You are very welcome!

 

On the ODDR: please note comments of bruce_karaffa about which pin of ODDR to use for the clock-enable (CE).  That is, in the image of the ODDR from UG903 that I showed you, you can toggle the D1 pin to stop the clock in the low state.  -or, you can toggle the D2 pin to stop the clock in the high state.  The stopped-state of the clock may be important to what you are doing.

 

    I(n) both cases the timing of the clock enable is monitored internally, therefore no explicit timing constraints are needed.

Since you mention using an 85MHz clock, timing constraints and formal timing analysis are probably needed.  As you learn about writing these constraints, it will be helpful to use the terminology “Single Data Rate (SDR) interface with the FPGA”.  The word, SPI, usually refers to an SDR interface with a slow clock (often too slow to need formal timing analysis). 

 

If the interface you are designing outputs both a clock and data to a device outside the FPGA then you have a Source-Synchronous SDR Output interface.  You will find a template of timing constraints needed for this interface in the Vivado XDC templates (under Flow Navigator, select “PROJECT MANAGER > Language Templates > XDC > Timing Constraints”).  Unfortunately, Xilinx has very limited description of these templates.  However, you’ll find many posts in this Forum by avrumw (aka god of timing analysis) that describe use of the constraints/exceptions found in the Vivado XDC templates.

 

Mark