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stefanot
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Registered: ‎06-27-2019

Timing constraints interactive debug

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Dear all,

I have a question that may be general. I am synthesizing an FPGA project (RFSoC with Xilinx's IPs and PL) using the .tcl script created by the GUI environment:
  vivado -mode batch -source script.tcl

The struct of this script is such that it first sets all the options and parameters, then the synthesis and implementation are launched in batch.
I got either warnings on the log or in the check_timing report that I would like to fix, but I cannot find the result of the application of the timing constraints I am using at the moment they are applied.
Additionally, if I try to apply the constraints from the tcl console on the implemented design, no errors are reported which means that the ports/pins I am addressing are correctly found.
Ideally I would like to do a sort of interactive constraint application to have a step-by-step debug, but I don't know if it possible and, if so, how.

Does anyone have any suggestion on how this could be achieved?
Any help would be greatly appreciated.

Best regards,
Stefano

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

What you are asking for cannot be done directly. But there are options.

The first thing is to find the synthesis log. In the GUI, in the bottom pane, select the Log tab, and make sure the tab on the bottom is selecting Synthesis

 

avrumw_0-1613689179489.png

In here you will see "Processing XDC Constraints" - it will then list all the files it is using and will give errors/warnings/info including line numbers in the respective files. If there is a problem with the XDC files you will see them here. The implementation log is in the Implementation tab, but it is less verbose when it comes to constraints.

You can also find these logs in the <project>/<project>.runs/synth_1/runme.log and <project>/<project>.runs/impl_1/runme.log

You can also see all the constraints applied to the design using the constraints window - with either the synthesized or implemented design open, select Window-> Timing Constraints. Here, in the "All Constraints" portion, it shows all the files it read and what constraints it understood from this file. If a constraint is malformed in the source file, it will not show up here - it is rejected by the parser. Looking through this list and comparing it to your .xdc source files can help you figure out what got missed.

Next, it is easy to "test" constraints on the second pass of the constraints - just open the synthesized design and start applying constraints. You can copy them line by line from your constraint files. You can use the order of files processed from the constraints window (for implemented designs).

For diagnosing problems in the first pass, you need to open the Elaborated design. This does a first pass synthesis (the elaborated design is never stored) - the elaboration is actually the first part of synthesis. When this is done, your in memory netlist is what is used for the application of the first pass of constraints. Again, you can copy and paste your constraints one by one from the .xdc files in to the Tcl console and see what happens. For the order of constraint files here, you should use the files and order of files shown in the synthesis log file.

Again, most problems (I would say all problems) should be visible in the log files. Applying constraints interactively to the elaborated or synthesized design is usually used for testing out constraints while you are developing them...

Avrum

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

We don't have anyway of knowing what the script itself is doing. From what you have told us we can't even figure out if it is scripted project mode or scripted non-project mode...

So there are multiple answers...

The log should be pretty clear - it will show where in the flow the warning messages are coming from. 

There is no built-in debug mechanism in the Tcl flow - the only way to "step through" these are manually - modify your script to stop (or pause) prior to each important step and do interactive stuff there. There are two ways I can think about - simply open the GUI and cut and paste each line  (or bunch of lines) of your script from a text editor into the GUI Tcl window. This will be identical in terms of results to running the script.

Alternatively you can modify your script to add "start_gui" at any point that you want to pause - the script will stop, open the GUI, and give you access to the Tcl command window with the complete context of the system as it is in the script. You can query stuff there, and then, to continue, type "stop_gui" - the GUI will stop and the script will continue.

But, that being said, there is a pretty common reason for the behavior you are describing... Take a look at this post on the fact that your XDC is read twice during the normal flow - once during synthesis and once after (either after synthesis or before implementation, depending on your flow). The two netlists (during synthesis, which is after elaboration, and after synthesis) are not identical. It is possible to construct constraints that only work with one version of the netlist (in your case the post-synthesis netlist) and not the other - in which case you can get warnings during synthesis, but after implementation everything is fine.

There are two main reasons for this - the name of something changes during synthesis and the way you specified the constraint isn't flexible enough to deal with the subtly different names. This was more common in earlier versions of Vivado (where there were more differences in the netlists), but is pretty rare these days (but still possible). The other reason is IP. Xilinx IP is synthesized "out-of-context" by default - which means that during your top level synthesis, any embedded IP is a black box. Only after synthesis (during/prior to implementation) are these black boxes filled in. This can result in things not being found during the top level synthesis. Take a look at this post on how constraints are used in the flow.

Avrum

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stefanot
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Registered: ‎06-27-2019

Dear Avrum,

thanks a lot for your feedback. What I meant in my original post is about a possibility to walk step by step in the xdc file, i.e. when the timing constraints are applied.

The script I was referring to is generated by the GUI and has the following structure:
[parameter settings, e.g. RTL file list, IP list, xdc list, synthesis options, implementation option, etc.]
# Create bit-file
set_property [current_fileset]
launch_runs impl_1 -to_step write_bitstream -jobs 28
wait_on_run impl_1

The actual job is executed when the last two lines are invoked and the application of the constraints (twice as you've mentioned) is done during these procedure that I cannot (or don't know how to) stop. The problematic constrains refer to invariant points, like i/o port that do not change during the implementation flow, in particular it's a bunch of set_input/output_delay to top level ports.
After the implementation is done, the check_timing reports that these ports do not have an input/output delay, but, if I apply the same constraint lines of my .xdc file in the tcl console, I got no errors.
For this reason, I was looking for a way to interactively apply the .xdc file at the point of the flow where it is actually executed to check whether there are special conditions that make the application of such constraints to fail.
Another possibility would be to increase the verbosity of the (internal) synthesis/implementation step from where I could check whether each single line of my .xdc is successfully applied.
These kind on information are not available on the log file... at least the one I am getting.

I hope this makes my first message a bit clearer.
Thanks in advance for any further help/suggestion.

Best regards, Stefano

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avrumw
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Guide
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Registered: ‎01-23-2009

What you are asking for cannot be done directly. But there are options.

The first thing is to find the synthesis log. In the GUI, in the bottom pane, select the Log tab, and make sure the tab on the bottom is selecting Synthesis

 

avrumw_0-1613689179489.png

In here you will see "Processing XDC Constraints" - it will then list all the files it is using and will give errors/warnings/info including line numbers in the respective files. If there is a problem with the XDC files you will see them here. The implementation log is in the Implementation tab, but it is less verbose when it comes to constraints.

You can also find these logs in the <project>/<project>.runs/synth_1/runme.log and <project>/<project>.runs/impl_1/runme.log

You can also see all the constraints applied to the design using the constraints window - with either the synthesized or implemented design open, select Window-> Timing Constraints. Here, in the "All Constraints" portion, it shows all the files it read and what constraints it understood from this file. If a constraint is malformed in the source file, it will not show up here - it is rejected by the parser. Looking through this list and comparing it to your .xdc source files can help you figure out what got missed.

Next, it is easy to "test" constraints on the second pass of the constraints - just open the synthesized design and start applying constraints. You can copy them line by line from your constraint files. You can use the order of files processed from the constraints window (for implemented designs).

For diagnosing problems in the first pass, you need to open the Elaborated design. This does a first pass synthesis (the elaborated design is never stored) - the elaboration is actually the first part of synthesis. When this is done, your in memory netlist is what is used for the application of the first pass of constraints. Again, you can copy and paste your constraints one by one from the .xdc files in to the Tcl console and see what happens. For the order of constraint files here, you should use the files and order of files shown in the synthesis log file.

Again, most problems (I would say all problems) should be visible in the log files. Applying constraints interactively to the elaborated or synthesized design is usually used for testing out constraints while you are developing them...

Avrum

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