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Visitor
Visitor
1,330 Views
Registered: ‎03-22-2019

Timing constraints not met

I am using Artix 7 fpga. What ever period I set, it is showing timing constraints not met. How to set correct period or timing constraints.timing.PNG

 

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Scholar
Scholar
1,320 Views
Registered: ‎08-07-2014

@girireddy,

What ever period I set, it is showing timing constraints not met.

Very wrong way to debug. And it should never be this way.

You clock should be more or less fixed and accordingly the design should be adapted.

Without the design details I cannot comment more.

------------FPGA enthusiast------------
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Visitor
Visitor
1,295 Views
Registered: ‎03-22-2019

Is it possible to see delay, power and frequency of the above design in vivado with applying any timing constraints

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1,267 Views
Registered: ‎06-21-2017

Your timing errors are hold time errors, not set up time errors.  Slowing your clock will not fix these.  You need to look at the failing paths and figure out why they are failing.

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Explorer
Explorer
1,263 Views
Registered: ‎07-18-2018

@girireddy,

 

To answer this question:

Is it possible to see delay, power and frequency of the above design in vivado with applying any timing constraints

 

Depending what you mean, yes.

 

You can open your implemented design, and apply a new clock or a new timing constraint. And then rerun the timing check, and it will reflect those changes. Now, if this is because of missing false paths, it might let you know it all works, but if those constraints allow the tool to do something different, you will have to reimplement to see those changes.

 

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