04-03-2019 12:26 AM
I am using Artix 7 fpga. What ever period I set, it is showing timing constraints not met. How to set correct period or timing constraints.
04-03-2019 01:07 AM - edited 04-03-2019 01:14 AM
What ever period I set, it is showing timing constraints not met.
Very wrong way to debug. And it should never be this way.
You clock should be more or less fixed and accordingly the design should be adapted.
Without the design details I cannot comment more.
04-03-2019 05:09 AM
Your timing errors are hold time errors, not set up time errors. Slowing your clock will not fix these. You need to look at the failing paths and figure out why they are failing.
04-03-2019 06:26 AM
To answer this question:
Is it possible to see delay, power and frequency of the above design in vivado with applying any timing constraints
Depending what you mean, yes.
You can open your implemented design, and apply a new clock or a new timing constraint. And then rerun the timing check, and it will reflect those changes. Now, if this is because of missing false paths, it might let you know it all works, but if those constraints allow the tool to do something different, you will have to reimplement to see those changes.