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Registered: ‎02-08-2017

Timing constraints of regenerated clocks from DCM

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Hello,

I can read in user guide 612 page 36 here that automatic constraints for the regenerated clocks are set and can be viewed in the report .bld file.

I have the attached configuration.I added the following constraint

 

NET clkp TNM_NET = "IN_MainCLK";

TIMESPEC TS_INCLK = PERIOD IN_MainCLK 5 ns HIGH 50 %;

However it seems that the synthesis tool (XST) removed this constraint. The .bld file says that the NET was removed. The .twr file say that 0 paths are covered by this constraint. The .par file didn't count for this constraint (ignored it).

My Question is:

1-Why this constraint has been ignored?

2- How to see constraints for the regenerateed clocks after DCM?

Thanks in Advance

XQ_3.PNG

 

 

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Guide
Guide
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Registered: ‎01-23-2009

Re: Timing constraints of regenerated clocks from DCM

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This is probably not so much a constraint issue, but a circuit structure issue.

 

If the NET was removed by synthesis, then it is most likely that the tool has decided it isn't needed. By definition, a clock is not needed if no logic is dependent on it; which means that no un-pruned flip-flops exist in the design that use the input or either of the two derived clocks.

 

The FPGA tools do significant pruning. This will occur if

  1) The flip-flop always holds a constant value

      - this can occur if it is, for example, always held in reset

  2) The flip-flop's output can't eventually effect an output

      - this can occur if an internal node is left unconnected, or if there is some downstream gating condition that gates the value of this flip-flop

 

Generally, these (and all other sources of unexpected pruning) become evident if you simulate the design. If a whole domain gets pruned out, you generally have some gross system level error; this will generally make the design not function and should be obvious in RTL simulations.

 

Of course, if the NET is pruned out in synthesis, then it cannot be constrained in ngdbuild (which is where the UCF file is read in).

 

Avrum

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Guide
Guide
5,721 Views
Registered: ‎01-23-2009

Re: Timing constraints of regenerated clocks from DCM

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This is probably not so much a constraint issue, but a circuit structure issue.

 

If the NET was removed by synthesis, then it is most likely that the tool has decided it isn't needed. By definition, a clock is not needed if no logic is dependent on it; which means that no un-pruned flip-flops exist in the design that use the input or either of the two derived clocks.

 

The FPGA tools do significant pruning. This will occur if

  1) The flip-flop always holds a constant value

      - this can occur if it is, for example, always held in reset

  2) The flip-flop's output can't eventually effect an output

      - this can occur if an internal node is left unconnected, or if there is some downstream gating condition that gates the value of this flip-flop

 

Generally, these (and all other sources of unexpected pruning) become evident if you simulate the design. If a whole domain gets pruned out, you generally have some gross system level error; this will generally make the design not function and should be obvious in RTL simulations.

 

Of course, if the NET is pruned out in synthesis, then it cannot be constrained in ngdbuild (which is where the UCF file is read in).

 

Avrum

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Explorer
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Registered: ‎02-08-2017

Re: Timing constraints of regenerated clocks from DCM

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I was running this design on Kintex 7 .. when I replaced the DCM with MMCM the constraint took effect
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Guide
Guide
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Registered: ‎01-23-2009

Re: Timing constraints of regenerated clocks from DCM

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I was running this design on Kintex 7 .. when I replaced the DCM with MMCM the constraint took effect
 
I am glad that solved your issue - it is a bit odd; the tools should have automatically converted the DCM to an MMCM...
 
But, it is worth pointing out that if you are working with Kintex-7, you might want to consider moving from ISE to Vivado. While there is a fairly steep learning curve, the benefits are worth it in the long run. To help in the transition, Xilinx has (or at least used to have) courses specifically designed for experienced ISE designers to migrate to Vivado; some of the Authorized Training Providers (like Hardent) still offer them...
 
 
Avrum
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Registered: ‎02-08-2017

Re: Timing constraints of regenerated clocks from DCM

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Thanks for this hint and guide, It is in my plan actually to migrate to vivade ... i think it is a matter of time
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