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Visitor bbergenf
Visitor
3,652 Views
Registered: ‎04-02-2009

Timing constraints on Interface where I am generating the clock output

Dear Users: 

I have a situation in my design that seems different from what I have seen in the timing constarints guide. The reference clock feeds the DCM but it's frequency is too low for the DCM to operate with feedback so there is no feedback on the DCM. The output of trhe DCM feeds some internal logic and also feeds an output pin that provides a clock to an external SDRAM (SDRAM_CLK). I have created a clock constraint to define the frequency of the input reference clock (AFE_REFCLK) that feeds the DCM. I also understand that ISE automatically figures out the frequency of clocks that come out of the DCM outputs. I want to define constraints on the SDRAM interface signals with respect to the clock that I output to the SDRAM. It seems that this results in warnings generate by ISE that say that no elements were found for the SDRAM_CLK.

I thought that I would not need to do something special to define SDRAM_CLK but it seems that ISE is confused. How do I create the XCF timing constraints for my situation.

Here is what I have now:

 

NET "afe_refclk" TNM_NET = afe_refclk;
TIMESPEC TS_afe_refclk = PERIOD "afe_refclk" 38 ns HIGH 50%;

 

NET SDRAM_FLSH_DQ* OFFSET = IN 24 ns BEFORE SDRAM_CLK;

NET SDRAM_FLSH_DQ* OFFSET = OUT 29 ns AFTER SDRAM_CLK;

 

 

Thank you for any help you can provide.

 

Bruce Bergenfeld

Synterix Technology

www.synterix.com

 

 

 

 

Bruce Bergenfeld
Synterix Technology Ltd.
www.synterix.com
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