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Visitor asiradek
Visitor
511 Views
Registered: ‎06-24-2019

Timing constraints valid only in synthesis, no object found in implementation

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Hi,

I tried to run synthesis and implementation with false path constraint set:

set_false_path -through [get_pins -hier -filter name=~*/instance1/port1] -through [get_pins -hier -filter name=~*/instance2/port2]

 

The synthesis works fine without any warning, but in implementation I can see critical warnings:

[Vivado 12-508] No pins matched 'get_pins -hier -filter name=~*/instance1/port1'.
[Vivado 12-508] No pins matched 'get_pins -hier -filter name=~*/instance2/port2'.

First of all, I assume that applying set_false_path constraint only for synthesis is not enough. Is that right?

Unfortunately, I was not able to track signals in implementated design. I also tried to set KEEP attributes to ports in RTL, but without any success. I was able to prevent port renaming using MARK_DEBUG attribute (set from XDC), but I do not want to prevent optimization. Is there any way how to apply a constraint while optimization is still enabled?

Thank you.

Best regards,

Radek

 

 

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1 Solution

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Guide avrumw
Guide
437 Views
Registered: ‎01-23-2009

Re: Timing constraints valid only in synthesis, no object found in implementation

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What you are asking is basically impossible.

You are asking to apply constraints through specific pins of a combinatorial network, but at the same time you don't want to reduce the optimizations that synthesis can do to this combinatorial network. You can't have both.

When synthesis encounters a combinatorial network, it maps the functionality to a collection of combinatorial cells within the CLB. As part of this, individual nets/pins can cease to exist - they aren't just renamed, they are merged with other signals and simply no longer exist. Any signal that "looks like" the original net/pin is probably not the same functionality and there is no way to prove that a constraint that was valid for the original net/pin is valid for this new net/pin.

If you need to apply constraints to a net/pin, then you need to preserve it. This would be done with a combination of synthesis options like "DONT_TOUCH" and keeping hierarchy. Both of these will limit the optimizations that synthesis can do with a combinatorial network.

So you have to choose one or the other - you can't have both.

Alternatively, you need to find other ways of specifying your constraints. With a few exceptions (register duplication and rebalancing) registers are not modified by the synthesis process - if you can specify your constraints from register to register then they will be usable both pre- and post-synthesis.

Finally, constraints are independently processed during the synthesis and implementation processes. The fact that the constraints were properly accepted during synthesis will only affect the synthesis process. When the implementation process starts, the constraints are re-read from the XDC files (or a different set of XDC files if you manage your constraints files with the USED_IN_SYNTHESIS/USED_IN_IMPLEMENTATION properties) - the constraints read in during implementation must be compatible with the post-synthesis netlist, including any optimizationd performed by synthesis.

Avrum

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8 Replies
Xilinx Employee
Xilinx Employee
505 Views
Registered: ‎05-14-2008

Re: Timing constraints valid only in synthesis, no object found in implementation

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get_pins -hier -filter name=~*/instance1/port1
get_pins -hier -filter name=~*/instance2/port2

If you run the above two commands in the Implemented design, what do you get?

If it says "No pins matched xxx", search in the implemented design to see if the two pins exist or with a different name.

When we know why they cannot be found in implementation, we can then try to figure out a solution.

-vivian

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Visitor asiradek
Visitor
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Registered: ‎06-24-2019

Re: Timing constraints valid only in synthesis, no object found in implementation

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Hi Vivian,

Thank you for your reply. In implemented design I got no pin matched warning.

I tried to search the implemented design command below and I found the some pins:

get_pins -hier -filter name=~*port1*
.../instance1/unexpected_instance/port1
.../instance2/port2_inferred_i_1/O
.../instance2/port2_inferred_i_1/I0
.../instance2/port2_inferred_i_1/I1
.../instance2/port2_inferred_i_10/O
.../instance2/port2_inferred_i_10/I0
.../instance2/port2_inferred_i_10/I1
.../instance2/port2_inferred_i_10/I2
...

I have also port3 for another constraint which I was not able to find at all.

What does the inferred suffix means? How can I find out a new name of port3?

I set KEEP attribute to all mentioned ports in RTL. Is this attribute still supported in 2018.2?

(* keep = "true" *) input   port1,


Thank you.

Radek

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Xilinx Employee
Xilinx Employee
474 Views
Registered: ‎05-14-2008

Re: Timing constraints valid only in synthesis, no object found in implementation

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Keep is supported but only for Synthesis. So it does not resolve your issue.

What are the port1, port2, port3 pins in your design?

Could you provide some details?

Can you show us the schematic of those pins in the synthesized design?

You probably need the schematic to help you understand what happened to those pins during Implementation, by comparing the schematic in the synthesize design and in the implemented design.

You can search by not only the names of those pins, but also the cells that are connected to those pins.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Observer dror_m
Observer
465 Views
Registered: ‎06-19-2019

Re: Timing constraints valid only in synthesis, no object found in implementation

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try to add '*' at the port:
set_false_path -through [get_pins -hier -filter name=~*/instance1/port1*] -through [get_pins -hier -filter name=~*/instance2/port2*]
because the implementation is changing the synthesis for optimization, it can duplicate registers and therefor changing the name by adding suffix.
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Visitor asiradek
Visitor
453 Views
Registered: ‎06-24-2019

Re: Timing constraints valid only in synthesis, no object found in implementation

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Hi Vivian,

Unfortunately, I am not allowed to share details about the design. All the ports pins are internal module ports.

I tried to find those ports in synthesized design but I was not able to find them. There is no pins matched warning. However, I can't see any warnings during synthesis. Does it mean that constraints where applied to synthesis before renaming and optimization? Is there any way how to obtain renamed nets/pins automatically? I would expect that constraints applied during elaboration / synthesis will be automatically propagated to the implementation.

Radek

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Guide avrumw
Guide
438 Views
Registered: ‎01-23-2009

Re: Timing constraints valid only in synthesis, no object found in implementation

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What you are asking is basically impossible.

You are asking to apply constraints through specific pins of a combinatorial network, but at the same time you don't want to reduce the optimizations that synthesis can do to this combinatorial network. You can't have both.

When synthesis encounters a combinatorial network, it maps the functionality to a collection of combinatorial cells within the CLB. As part of this, individual nets/pins can cease to exist - they aren't just renamed, they are merged with other signals and simply no longer exist. Any signal that "looks like" the original net/pin is probably not the same functionality and there is no way to prove that a constraint that was valid for the original net/pin is valid for this new net/pin.

If you need to apply constraints to a net/pin, then you need to preserve it. This would be done with a combination of synthesis options like "DONT_TOUCH" and keeping hierarchy. Both of these will limit the optimizations that synthesis can do with a combinatorial network.

So you have to choose one or the other - you can't have both.

Alternatively, you need to find other ways of specifying your constraints. With a few exceptions (register duplication and rebalancing) registers are not modified by the synthesis process - if you can specify your constraints from register to register then they will be usable both pre- and post-synthesis.

Finally, constraints are independently processed during the synthesis and implementation processes. The fact that the constraints were properly accepted during synthesis will only affect the synthesis process. When the implementation process starts, the constraints are re-read from the XDC files (or a different set of XDC files if you manage your constraints files with the USED_IN_SYNTHESIS/USED_IN_IMPLEMENTATION properties) - the constraints read in during implementation must be compatible with the post-synthesis netlist, including any optimizationd performed by synthesis.

Avrum

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Xilinx Employee
Xilinx Employee
423 Views
Registered: ‎05-14-2008

Re: Timing constraints valid only in synthesis, no object found in implementation

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As Avrum suggested, the pins you're using in the set_false_path are part of a combinational logic. Then this can explain why your constraint is taken by Synthesis but not in Implementation.

In Synthesis, the XDC is read after the elaboration process. At this stage the hierarchical pin names are generally as what they're described in RTL. So the tool is able to "find" them. In the subsequent Synthesis processes, when optimizations are done across hierarchy boundaries, those pins are renamed or even totally changed. So you're not able find them in the Synthesized design. And, when Implementation starts, the XDCs are re-loaded and the Implementation complains about the pins not found.

Please follow Avrum's advice on how to revise your constraint.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
Observer dror_m
Observer
405 Views
Registered: ‎06-19-2019

Re: Timing constraints valid only in synthesis, no object found in implementation

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regarding what Avrum said, the way i am specified false path is by defining general rule to false path and then use it at the design:
1. `define FALSE_PATH_NET (* THIS_NET_IS_FALSE = "TRUE", dont_touch = "true" *)
2. `FALSE_PATH_NET logic <logic_name>;
3. in the XDC: set_false_path -through [get_nets -hier -filter {THIS_NET_IS_FALSE == TRUE}]
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