UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
112 Views
Registered: ‎04-11-2016

Timing constraints with debug

Jump to solution

Hi,

If a design passed timing but after adding debug timing didn't pass. I have following questions:

1. can we still trust such design(without debug pass and with debug not pass) for hardware debugging?

2. If we don't want to debug, is the generated bitfile without timing pass works same as bitfile with timing pass?

 

P.S. I am working at 400 MHz.

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
106 Views
Registered: ‎01-16-2013

Re: Timing constraints with debug

Jump to solution

Hi @fpgalearner 

If there is timing violations that means this design is not good for hardware run.

When you add debug you are actually adding new functionality in your design which results into more utilization. This design change (ILA insertion) have impact on overall Implementation so the results with and without ILA for implementation cannot be same and this is expected.

So before you take ILA inserted design to hardware for board level debugging you need to close the timing and then generate bitstream, with timing violated design you cannot expect the results.

With ILA and without ILA bitstream is not same. But having said that if your both builds (with/without ILA) passed timing and then if you validate the bitfile on board functionality should be same. ILA should not change the design functionality thats the baseline.

BTW ILA should be used for debugging purpose, once the purpose is solved its always better to remove ILA from design for production build.

Thanks,
Yash

 

1 Reply
Moderator
Moderator
107 Views
Registered: ‎01-16-2013

Re: Timing constraints with debug

Jump to solution

Hi @fpgalearner 

If there is timing violations that means this design is not good for hardware run.

When you add debug you are actually adding new functionality in your design which results into more utilization. This design change (ILA insertion) have impact on overall Implementation so the results with and without ILA for implementation cannot be same and this is expected.

So before you take ILA inserted design to hardware for board level debugging you need to close the timing and then generate bitstream, with timing violated design you cannot expect the results.

With ILA and without ILA bitstream is not same. But having said that if your both builds (with/without ILA) passed timing and then if you validate the bitfile on board functionality should be same. ILA should not change the design functionality thats the baseline.

BTW ILA should be used for debugging purpose, once the purpose is solved its always better to remove ILA from design for production build.

Thanks,
Yash