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Adventurer
Adventurer
243 Views
Registered: ‎11-14-2018

Timing default after using MMCM

In my project, I need to use MMCM to get a 50 MHz clock, but after adding the clock constraint with the constraints wizard, I executed the report timimg summary and found that there are two clock defaults.

The result is shown below:

捕获1.JPG捕获2.JPG

MMCM.zip is a complete project that has the same problems as in the second picture.

The timing constraint file and the timing report result have been uploaded. I hope I can get your help.

 

 

thanks!!

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1 Reply
Historian
Historian
233 Views
Registered: ‎01-23-2009

Re: Timing default after using MMCM

The virtual clock was created explicitly by your constraint file. All your inputs are constrained with respect to this virtual clock.

The constraint file does not contain a create_clock for the "real" primary clock of your FPGA - presumably this is provided by the clocking wizard's scoped constraint file.

Thus, you have specifically created these inter-clock paths. What you have done is unusual (probably incorrect) - the constraints for the inputs and outputs are normally related to the primary clock of the FPGA.

Avrum

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