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Visitor michaeldevid
Visitor
5,523 Views
Registered: ‎08-17-2012

Timing erros with RAMB16_S9_S9 and two different clocks

I’m an intern and designing an Gigabit Ethernetcamera with the Spartan-6 SP605 Evaluation Platform (XC6SLX45T). The camera data is written to the RAMB16_S9_S9  component with a clock of 48MHz. The data is read with a clock of 125MHz. But the code is designed so they never read or write from the same address.

 

The RAMB16_S9_S9 component is a dual clock RAM component witch should operate without problems with two different clock signals. But when I generate the Timing report I get these timing errors:

 

Met

Constraint

Check

Worst Case Slack

Best Case Achievable

Timing Errors

Timing Score

No

TS_CLOCK_GENERATION_clkout0 = PERIOD TIMEGRP "CLOCK_GENERATION_clkout0" TS_CLK_IN1 / 4.625 HIGH 50% INPUT_JITTER 0.37037 ns

SETUP HOLD

-4.506ns 0.293ns

44.056ns

77 0

252488 0

No

TS_CLOCK_GENERATION_clkout2 = PERIOD TIMEGRP "CLOCK_GENERATION_clkout2" TS_CLK_IN1 / 1.76190476 HIGH 50% INPUT_JITTER 0.37037 ns

SETUP HOLD

-1.639ns 0.462ns

55.440ns

11 0

16145 0

Yes

TS_CLK_IN1 = PERIOD TIMEGRP "CLK_IN1" 37.037 ns HIGH 50% INPUT_JITTER 0.37037 ns

MINLOWPULSE

27.036ns

10.000ns

0

0

 

Now the strange thing is that my design does work, it send and receives packets and I can view the camera image. Now when I change the clock of PORT A from the 48MHz to the same as PORT B thus the 125MHz signal.  I get these timing errors:

 

Met

Constraint

Check

Worst Case Slack

Best Case Achievable

Timing Errors

Timing Score

No

TS_CLOCK_GENERATION_clkout0 = PERIOD TIMEGRP "CLOCK_GENERATION_clkout0" TS_CLK_IN1 / 4.625 HIGH 50% INPUT_JITTER 0.37037 ns

SETUP HOLD

-1.563ns 0.268ns

20.512ns

8 0

10582 0

Yes

TS_CLK_IN1 = PERIOD TIMEGRP "CLK_IN1" 37.037 ns HIGH 50% INPUT_JITTER 0.37037 ns

MINLOWPULSE

27.036ns

10.000ns

0

0

Yes

TS_CLOCK_GENERATION_clkout2 = PERIOD TIMEGRP "CLOCK_GENERATION_clkout2" TS_CLK_IN1 / 1.76190476 HIGH 50% INPUT_JITTER 0.37037 ns

SETUP HOLD MINPERIOD

19.331ns 0.521ns 19.291ns

1.690ns 1.730ns

0 0 0

0 0 0

 

This is the code for the RAM block:

 

	RAMB16_S9_S9_001 : RAMB16_S9_S9
	port map (
		DOA => open,      -- Port A 8-bit Data Output
		DOB => DOB(J),      -- Port B 8-bit Data Output
		DOPA => open,    -- Port A 1-bit Parity Output
		DOPB => open,    -- Port B 1-bit Parity Output
		ADDRA => WPTR(10 downto 0),  -- Port A 11-bit Address Input
		ADDRB => RPTR(10 downto 0),  -- Port B 11-bit Address Input
		CLKA => PIX_CLK,    -- Port A Clock
		CLKB => CLK,    -- Port B Clock
		DIA => STREAM_DATA,      -- Port A 8-bit Data Input
		DIB => x"00",      -- Port B 8-bit Data Input
		DIPA => "0",    -- Port A 1-bit parity Input
		DIPB => "0",    -- Port-B 1-bit parity Input
		ENA => '1',      -- Port A RAM Enable Input
		ENB => '1',      -- PortB RAM Enable Input
		SSRA => '0',    -- Port A Synchronous Set/Reset Input
		SSRB => '0',    -- Port B Synchronous Set/Reset Input
		WEA => WEA(J),      -- Port A Write Enable Input
		WEB => '0'       -- Port B Write Enable Input
	);

The read address/pointer is controlled by this code:

WPTR_GEN_001: process(ASYNC_RESET, PIX_CLK)
begin
	if(ASYNC_RESET = '1') then
		WPTR <= (others => '0');
	elsif rising_edge(PIX_CLK) then
		if(STREAM_DATA_VALID = '1') then
			WPTR <= (WPTR + 1) and PTR_MASK; 
--increse the address at every data clock end if; end if; end process;

Now I’m wondering why this RAM component gives these timing errors. I have attached my .TWX file so you can see more information about the timing errors.  

 

Thanks,

 

Michael

 

Using ISE v. 14.2

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
5,507 Views
Registered: ‎07-16-2008

Re: Timing erros with RAMB16_S9_S9 and two different clocks

In 14.1/14.2, there's a tool bug which mixes up the BRAM/FIFO's RDCLK and WRCLK requirement.

Please check out the following Design Advisory Answer.

http://www.xilinx.com/support/answers/51580.htm

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