01-07-2021 07:31 AM
I have a MMCM in my design that takes a 62.5MHz clock as input and generates three clocks: 100MHz, 50MHz and 200MHz.
Timing fails on a path clocked at 100MHz with a WNS of -1.06ns, so the design should be capable of running at 90.4MHz. When I change the settings of the MMCM and configure 90MHz instead of 100MHz, I get a WNS of -5.4ns (i.e. 60.6MHz). This result is beyond my understanding.
As I interpret the timing report, Vivado is capable of fitting the design at 90MHz when the clock is configured at 100MHz, but not when the same clock is set to 90MHz. Does anyone have a clue on how I could get this design running at 90MHz?
01-08-2021 02:18 AM - edited 01-08-2021 02:21 AM
At 100MHz, the failures are intra-clock.
At 90MHz, failures are both inter-clock and intra-clock. WNS is -5.3 instead of -5.4 as I said in my first message, I did several changes in fitter options, without success. WNS of -5.3 is with the same fitter options as the fit done at 100MHz.
I was naively thinking that slowing down the 100MHz clock would have solved my timing issues.
01-08-2021 05:11 AM
Without the full timing report, this is only speculation but the intra-clock paths are probably the same for both the 100MHz and 90MHz cases. Adding pipeline registers to these paths my reduce both the number of logic stages between registers and reduce the routing delay between registers, allowing the logic to run on a faster clock. As for the inter-clock paths, are you using proper clock domain crossing techniques and constraints?
Also, what logic family are you targeting? 7-series or higher should be able to reach 100MHz fairly easily.
01-21-2021 02:11 AM
Thanks for your help.
Adding registers was the last option I wanted to explore. I finally changed the parameters of my design and was able to slow down the clock for my critical block. It now passes all the timings!
But this still puzzles me why Vivado reaches 90MHz when the clock is set to 100MHz but is not able to do it when slowing it down to 90MHz.