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Adventurer
Adventurer
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Registered: ‎03-02-2015

Timing failure in DDR3 Design

Hi,

 

Continuation from this thread : Error

 

I have a design which uses MIG ip.I added some user modules & i could get it to implement successfully.But in that design,i had differential system clock & reference clock.(4 diff sys clk + 1 diff ref clock.)

 

Earlier all these diff. clock inputs were inputs to my top module,now i wanted to generate those clocks internally by using clocking wizard.

 

I changed settings in MIG GUI to NO BUFFER option & am using a cascade of MMCM's to generate these clocks.

Now i am able to implement it successfully,but it is saying -

 

CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements.

 

Earlier without any MMCMs & option selected as differential in my MIG ip core,the design wasn't facing any such issues.I am getting this timing issue only after adding MMCMs to my design.

 

i've seen the timing report & as expected it is coming from the cascade of MMCMs that i have.

 

clock_gen_1 is a MMCM which takes a input clock of 337.5 & gives 200 MHz(clocK_out1) & 168.75 MHz (at clock_out2 & clock_out3).

clock_gen_2 is a MMCM which takes a input from output  clock of clcok_gen_1.


Timing Report :

Inter clock table:
From - clk_out1_clock_gen2_1
To      - clk_out2_clock_gen1

 

Setup :

WNS -> -5.693 ns;TNS -> -666.413 ns; TNS failing end points -> 130;Total end points -> 152

Hold:

WNS -> 0.916 ns, TNS -> 0 ns;TNS failing end points -> 0;Total end points -> 130

 

What could be the problem for this ?

Do i need to add any additional constraints ?

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