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Observer
Observer
8,233 Views
Registered: ‎04-16-2009

Timing getting worse after setting IOB = true

Hi All,

           In order to improve IO timings i have set IOB ( map flip flop to IOB flop) but the results from timing analysis

are worse compared to when IOB was set to false. I went through the both reports and found that ILOGIC is taking 

more delay compared to SLICE(without IOB = true) is this behaviour correct? I expect delay should be less when using

IO flop  .

Please share your thoughts. 

      

With IO flop

 

ILOGIC_X1Y99.DDLY    net (fanout=1)        5.538   sdram_din_1_IBUF

 

Without IO flop 

 

 SLICE_X102Y128.BX    net (fanout=1)        4.537   sdram_din_13_IBUF

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Professor
Professor
8,225 Views
Registered: ‎08-14-2007

It is possible for a carefully placed slice flip-flop to have a better setup time than

the IOB flip-flop, however I don't think the difference should be as large as you are

seeing.  I suspect that the IOB flip-flop has its delay element (betwen the pad

and flip-flop D) enabled to guarantee 0 hold time.  You didn't mention which family

of FPGA you're using.  For Spartan 3,Virtex 2, and older parts the default for

IOB input flops is to insert this delay and you need to turn it off using the

NODELAY attribute.  It's also possible that XST would automatically remove

the delay element if you have a timing constraint on the input setup.

 

HTH,

Gabor

-- Gabor
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Observer
Observer
8,197 Views
Registered: ‎04-16-2009

Hi ,

           I am using Virtex 5 and IOBDELAY is set to NONE hence it should use delay and i have also opened it in FPGA Editor and it shows it is not using it . Also from FPGA editor it can been seen that path from IOB to ILOGIC is very near than the Slice so the timing numbers should be less considerably .

 

Regards

Sudarshan

 

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Professor
Professor
8,194 Views
Registered: ‎08-14-2007

Two things:

 

1) you didn't show the complete path for the timings reported.  Are you talking about the delay

from the pad to the input flip-flop?  If not (i.e. path from the flip-flop to the next element in the

circuit) placing the input flop in the IOB could easily make timing worse by making the routing

path longer.

 

2) Although the route from the pad to the IOB flip-flop is dedicated and short, the IOB flip-flop

itself is not exactly like a fabric flip-flop and could add to the setup time from the pad.  I

haven't tried this in Virtex 5, but in some other FPGA families the setup from pad to the

IOB flip-flop is not as good as the setup from pad to the nearest fabric flip-flop.

 

Regards,

Gabor

-- Gabor
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Observer
Observer
8,153 Views
Registered: ‎03-02-2009

Hi ,

 

I just would like to add a point here, correct me if I am wrong.

 

As far as IOB flip flop and flip flop in a slice is considered,  flip flop in a slice will always give better timing result than IOB flip flop if as long as we are just talking about on chip delays. IOB flip flops are recommended to break off chip delay path ( path between PCB and IOB of FPGA) .

Thus as long as we are just talking about delays inside FPGA, delay between logic and slice will always be less than  delay between logic and IOB. (Although there are many other factors like placement of slice etc which are not considered here..)

 

Regards,

Onkar Patki

Message Edited by patkionkar on 01-10-2010 07:18 PM
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Newbie
Newbie
7,738 Views
Registered: ‎04-09-2010

ILOGIC_X1Y99.DDLY means the input of IOB register is sourcing from IODELAY primitive.  There is another dedicate route from PAD to IOB register input directly which named "D". You can see the IODELAY configration in FPGA edtior. I doubt the delay mode of IODELAY primitive is DEFAULT mode.  If the delay mode is DEFAULT mode, some extra delay is added for zero hold time of input clock.

 

 

Message Edited by gaoxj on 04-09-2010 06:39 PM
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