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Visitor morlerm
Visitor
2,753 Views
Registered: ‎04-20-2016

Timing met errors in place and route simulation

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Hello,

In my design i have constraints over each clock in it and i run smart explorer to meet timing (hold and setup),however after finding the most suitable strategy when it is place and route simulated i get too many hold and setup errors

is there something wrong in working with smart explorer to find the most suitable strategy ?
if timing is already met with a strategy what would cause errors in the par simulation

 

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Historian
Historian
4,953 Views
Registered: ‎01-23-2009

Re: Timing met errors in place and route simulation

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If I understand what you are saying, you have a design that

  - has proper constraints (at least on the clocks)

  - meets timing

     - it has a timing score of 0

     - you need to use smart_explorer to get the timing score of 0

  - you are doing simulation on the post-place and route netlist with full timing

  - you are getting messages from the simulator regarding setup and hold violations

 

If so, there are a couple of things to think about.

 

First, I wouldn't worry about smart explorer - it doesn't matter that you used it to get timing closure, only that you did get timing closure.

 

There are two possibilities (that I can think of)

 

1) You have some unconstrained paths that are failing timing. In trce, enable the unconstrained path report and make sure that all "real" paths are correct

2) You are getting timing errors on known asynchronous paths. When you have (say) a Clock Domain Crossing circuit, this does not avoid setup and hold violations, it merely makes the design work (most of the time) in spite of these violations. The simulation tool will still report the violations, but if the ASYNC_REG property is set on the flip-flops that fail setup/hold checks, then these flip-flops will not go unknown (X), so your system will continue to operate

3) Your testbench circuits are not properly mimicking the system as you constrained it

  - your clock period is smaller than your constraints

  - your inputs are not arriving within the timing windows specified by the OFFSET IN commands

 

In general, you have to look at what flip-flops are generating the setup/hold violations and figure out why.

 - are they the endpoints of normal static timing analysis paths (paths where the startpoint and endpoint are clocked by the same or related clocks)?

 - are they endpoints that receive signals combinatorially from input pins?

 - are they flip-flops involved in clock domain crossing circuits?

 - are these violations only near system startup or the deassertion of reset, or are they at all times?

 

Starting from these questions will lead us further.

 

Avrum

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Scholar austin
Scholar
2,745 Views
Registered: ‎02-27-2008

Re: Timing met errors in place and route simulation

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m,

 

Have you checked for unrelated clocks are to be ignored?  Vivado assumes all clocks are related, unless they are declared otherwise.

 

If there is no data crossing between a clock A and a clock B, they are unrelated, and an ignore timing constraint from A to B, and another for B to A may be needed.  Also read up on false paths as well.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
Historian
4,954 Views
Registered: ‎01-23-2009

Re: Timing met errors in place and route simulation

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If I understand what you are saying, you have a design that

  - has proper constraints (at least on the clocks)

  - meets timing

     - it has a timing score of 0

     - you need to use smart_explorer to get the timing score of 0

  - you are doing simulation on the post-place and route netlist with full timing

  - you are getting messages from the simulator regarding setup and hold violations

 

If so, there are a couple of things to think about.

 

First, I wouldn't worry about smart explorer - it doesn't matter that you used it to get timing closure, only that you did get timing closure.

 

There are two possibilities (that I can think of)

 

1) You have some unconstrained paths that are failing timing. In trce, enable the unconstrained path report and make sure that all "real" paths are correct

2) You are getting timing errors on known asynchronous paths. When you have (say) a Clock Domain Crossing circuit, this does not avoid setup and hold violations, it merely makes the design work (most of the time) in spite of these violations. The simulation tool will still report the violations, but if the ASYNC_REG property is set on the flip-flops that fail setup/hold checks, then these flip-flops will not go unknown (X), so your system will continue to operate

3) Your testbench circuits are not properly mimicking the system as you constrained it

  - your clock period is smaller than your constraints

  - your inputs are not arriving within the timing windows specified by the OFFSET IN commands

 

In general, you have to look at what flip-flops are generating the setup/hold violations and figure out why.

 - are they the endpoints of normal static timing analysis paths (paths where the startpoint and endpoint are clocked by the same or related clocks)?

 - are they endpoints that receive signals combinatorially from input pins?

 - are they flip-flops involved in clock domain crossing circuits?

 - are these violations only near system startup or the deassertion of reset, or are they at all times?

 

Starting from these questions will lead us further.

 

Avrum

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Visitor morlerm
Visitor
2,731 Views
Registered: ‎04-20-2016

Re: Timing met errors in place and route simulation

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thanks austin for your reply,

I am using ISE doesn't make any difference in this case ?, I did rechekc even now all the clocks are constrained and they all come from the same DCM,

how do i read up on false paths ?

 

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Visitor morlerm
Visitor
2,728 Views
Registered: ‎04-20-2016

Re: Timing met errors in place and route simulation

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thanks avrumw for your reply,

after checking the first point i do seem to have unconstrained paths and some of them are falling in time indeed !, thanks 

for the second point i do have a fifo with different read and write clocks but i don't write and read at the same time, first i write after the writing is done i start reading should i still get timing violations ?

 

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Historian
Historian
2,725 Views
Registered: ‎01-23-2009

Re: Timing met errors in place and route simulation

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for the second point i do have a fifo with different read and write clocks but i don't write and read at the same time, first i write after the writing is done i start reading should i still get timing violations ?

 

If the read clock and write clock are different then you can get timing violations on any read or write operation, as the FIFO updates its internal pointers (it also depends on how the FIFO is implemented - it may be different for the built-in FIFO rather than a block RAM or distributed RAM based FIFO). The violations here, though, are expected, and, assuming the FIFO is built properly, will not cause any failure.

 

Avrum

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