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776 Views
Registered: ‎11-03-2019

Timing path in elaborated design

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Hello,

I followed this guide(Chapter 6 ”Using the Elaborated View to Optimize the RTL “ )to find the worst path in RTL.

The schematic after synthesis looks well , but the schematic in elaborated missed many cells and nets. After I selected the start and end cells and clicked "Expand Cone to Selected Cells", almost all things in the design appears. I'm sure some of those are not on the path.

How can I show the schematic which only contains the chosen path in elaborated design?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

710488056@qq.com wrote:
Thank for your kindly reply.
With complex combinational logics, it's hard to find the path from endpoint and start point, because some cells drive multiple cells and be driven by multiple cells.

That's true. I'm not aware of a script for this.

This is a method to give a hint on where the large logic levels come from and what the RTL logics and connections look like. 

Usually this analysis is not only about a single path, but a group of paths that is referring to an always block or a procedure in your RTL code, for example.

When you have the startpoint and the endpoint in the synthesized design, you probably have got the idea which part in the code this path is referring to. The "Go to source" in the right-click menu will cross-probing to the exact RTL source file. You can expand the schematic in the elaborated design based on your understanding of the corresponding RTL code.

-vivian

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

It is the RTL level schematic in the elaborated design so the "cells" looks different from the synthesized design.

UG906 gives the following:

"After selecting the startpoint and endpoint cells of the critical path, you can visualize the
equivalent path in the elaborated view by opening a schematics of the selected cells and
expanding the logic from the endpoint pin back to the startpoint."

Do not use the "Expand Cone" function as it will expand everything.

And make sure that the start and end cells you selected do make a timing path. This means there is no sequential cells between them.

Thanks

Vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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746 Views
Registered: ‎11-03-2019
Thank for your reply, but how could I expanding the logic from the endpoint pin back to the startpoint.
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Guide
Guide
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Registered: ‎01-23-2009

If you really want to see a schematic of a path (in the elaborated or synthesized design), you need to "get" that path and then generate a schematic of it. There are tons of ways of doing this, but the easiest is probably through a combination of a Tcl command and the GUI.

To get the path, have the tool generate a report of the path. Again, there are multiple ways of doing this, but the easiest way is

report_timing -name my_path -from <startpoint> -to <endpoint>

When you do this, the tool will open a new tab (named  my_path) with the timing results from that timing report; it will show a table with the startpoint, endpoint and slack (and some other stuff). With no other options it will just show this path and just on one timing corner, but you can add other options to change that.

This table is "active" - you can click on the path to select it, and then right click and select "Show Schematic" (or just press F4). This will generate a schematic of the path showing just the path - the starpoint, the endpoint and all the cells and wires between them. From here, you can use the schematic viewer to add other stuff if you want, but you are starting with what you asked for - the complete path and no other cells.

Avrum

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623 Views
Registered: ‎11-03-2019

Thank for your reply.
I know how to show the path in synthesis schematic.I mean that  I followed UG906 to show the path in elaborated design, but found the path is incomplete while it‘s complete in synthesis schematic.

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Guide
Guide
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Registered: ‎01-23-2009

I know how to show the path in synthesis schematic.I mean that  I followed UG906 to show the path in elaborated design, but found the path is incomplete while it‘s complete in synthesis schematic.

I don't understand...

The mechanisms for viewing the schematic of a path is exactly the same in an elaborated or a synthesized design - if you can do it in the synthesized design, you should be able to do the exact same steps in the elaborated design.

I don't know what you mean by "the path is incomplete..."

Avrum

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Registered: ‎11-03-2019

In synthesis design, I chose the path,then press F4.

synthesis.png

Follow UG906,open elaborated design ,press F4.

elaborated.png

Obviously, many cells and nets were lost.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Most of the time the RTL schematic could not perfectly match the paths you see in the synthesized design, especially for complex combinational logics.

This example you gave is an expected result. You can then find the endpoint in this schematic and expand the paths by double clicking on the input pin(s) of the endpoint cell and input pin(s) of its driver cell......

Actually UG906 is suggesting select the startpoint and endpoint cells of the critical path,  open a schematics of the selected cells and expand the logic from the endpoint pin back to the startpoint.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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511 Views
Registered: ‎11-03-2019
Thank for your kindly reply.
With complex combinational logics, it's hard to find the path from endpoint and start point, because some cells drive multiple cells and be driven by multiple cells.
Is there any scripts to find it ?
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Xilinx Employee
Xilinx Employee
447 Views
Registered: ‎05-14-2008

710488056@qq.com wrote:
Thank for your kindly reply.
With complex combinational logics, it's hard to find the path from endpoint and start point, because some cells drive multiple cells and be driven by multiple cells.

That's true. I'm not aware of a script for this.

This is a method to give a hint on where the large logic levels come from and what the RTL logics and connections look like. 

Usually this analysis is not only about a single path, but a group of paths that is referring to an always block or a procedure in your RTL code, for example.

When you have the startpoint and the endpoint in the synthesized design, you probably have got the idea which part in the code this path is referring to. The "Go to source" in the right-click menu will cross-probing to the exact RTL source file. You can expand the schematic in the elaborated design based on your understanding of the corresponding RTL code.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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