10-06-2017 04:39 AM
We have been building designs for the ES part:
xcvu9p-flgb2104-2-i-es1
And are not migrating to the production part:
xcvu9p-flgb2104-2-i
There seems to be quite a difference in the timing performance in some places, including the output of the URAMs. The worst path on the same design after synthesis shows up some significantly higher delays in the timing reports i.e.
ES1 = URAM288 (Prop_URAM288_CLK_CAS_OUT_DOUT_B[55]) (r) 1.718
PROD = URAM288 (Prop_URAM288_CLK_CAS_OUT_DOUT_B[52]) (r) 2.154
This is 0.436ns worse and has a really significant impact on our ability to meet timing.
The version of Vivado we are using is:
Vivado v2017.2 (64-bit)
SW Build 1909853
IP Build 1909766
Some questions:
Regards,
Andy
10-06-2017 07:13 AM
A,
We do everything we can to get the speed files right. Any (all) ES numbers are only applicable to ES devices, and may change when the device goes to production. It is just as likely some numbers get smaller, as they get larger (no one is trying to be anything other than accurate).
Die size matters: smaller devices have different numbers that large die for some tiles, so trying to compare two different family members, ES or not, is like asking "my apple is green, why is my orange orange?" The answer: they are different.
It is, what it is.
10-06-2017 08:04 AM
Ok, I realise they are different. Can you tell me if the speed files in 2017.2 are the final values for the production silicon?
Andy
10-06-2017 08:13 AM
If they are for the production part number, they are final.
If they are for a ES release, they are the best quality possible before production release.