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Visitor bahadirozk
Visitor
123 Views
Registered: ‎02-06-2019

Timing, power and area analyze

Hello,

How do I analyze the timing, power and the are information of a design that I am doing in Vivado?

Below is an example showing the time and field information used, as I wanted in the picture.

Screenshot_1.png
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4 Replies
Xilinx Employee
Xilinx Employee
111 Views
Registered: ‎02-27-2019

回复: Timing, power and area analyze

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88 Views
Registered: ‎01-22-2015

Re: Timing, power and area analyze

@bahadirozk 

Timing is a complex subject and there are many timing paths in a typical design.  As yangc suggests, first read UG906.  As explained in UG906, timing path reports give you delay associated with combinational logic (and other logic) in your design.

Area/resource utilization and an estimate of power usage can be obtained after you open the Vivado implemented design - by clicking on "Report Utlization" and "Report Power".
Utilization_reports.jpg

Cheers,
Mark

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Moderator
Moderator
74 Views
Registered: ‎11-04-2010

Re: Timing, power and area analyze

Hi, @bahadirozk ,

UG949 is also a good material for your reference.

You can begin with the doc and turn to forum when you have the detailed question.

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Visitor bahadirozk
Visitor
45 Views
Registered: ‎02-06-2019

Re: Timing, power and area analyze

thanks all of your replys. But I said timing it mean delay report. I want to learn delay report of my design. And I want to learn clock speed report of my design on Vivado.

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