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Visitor
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Registered: ‎12-25-2019

Timing problems at low clock

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Hi to all, I'm trying to practice Vivado 2019.2.
I made a simple circuit that takes a 100Mhz clock on the input pin, passes it to a pll which leads it to
400 Mhz.
The 400Mhz sent to a primary divisor by 1,000,000.
Each time the primary counter passes through zero, a second 8-bit counter are incremented.
Every time the primary meter reaches 500,000 I invert a signal which I then use as a DDR clock (2Khz) for the data form the 8 bit counter.
I can't eliminate the errors on Vivado's timing report related to the 2Khz clock (which is centered on the data), maybe I'm wrong the parameters on the xdc.
And I can not describe in xdc the clock at 2Khz shifted and centered on 8 bit data.
What I also want to describe on xdc with set_output_delay is an external 8 bit clocked register, which must sample the clocked data that comes from fpga (2Khz source sync),
whith a Tsetup of 2uSec, and a Thold of 1uSec.

 

entity top_TEST_LED is
Port ( clk_in_100M : in STD_LOGIC;
clk_to_LEDS: out STD_LOGIC;
led_out : out STD_LOGIC_VECTOR (7 downto 0);
key_in : in STD_LOGIC_VECTOR (1 downto 0));
end top_TEST_LED;

architecture Behavioral of top_TEST_LED is

signal to_leds:std_logic_vector(7 downto 0):=x"00";
signal clk_400M:std_logic;
signal qc:std_logic_vector (31 downto 0);
signal low_clk:std_logic:='0';

component PLL1 is
port(clk_in_PLL: in std_logic;
clk_out1: out std_logic;
clk_out2:out std_logic);
end component PLL1;

COMPONENT COUNTER1
PORT (
CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;

begin

mypll1: PLL1 port map (
clk_in_PLL=> clk_in_100M,
clk_out1=>clk_400M,
clk_out2=>open
);
mycounter1:COUNTER1 port map (
CLK=>clk_400M,
Q=>qc
);

process (clk_400M)
begin
if rising_edge(clk_400M) then
if (qc=x"00000000") then
to_leds<=std_logic_vector( unsigned(to_leds) + 1 );
end if;
if (qc=x"0007a11f") then
low_clk<=not low_clk;
end if;
end if;
end process;
led_out<= not to_leds;
clk_to_LEDS<=low_clk;

end Behavioral;

 

 

I attach the project.

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1 Solution

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Highlighted
264 Views
Registered: ‎01-22-2015

Re: Timing problems at low clock

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@thieulam 

Welcome!  

Lots of things in your post for us to discuss.

First, your VHDL low_clk is not a clock.  Even though it looks like a clock, it is only a VHDL signal because it has not been placed in the FPGA clock tree.  -and your create_generated_clock constraint for low_clk needs fixing.

A good way to generate a slow clock is to route a fast clock through a clock buffer (eg. BUFGCE) that has a clock enable, CE, pin.  Then, by properly toggling CE, you can create a slow clock that is in the FPGA clock tree.  This method is described by Avrum in <this> post.  

Next, the create_generated_clock constraint for the slow clock is described by Avrum in <this> post.  

Once your slow clock is placed in the FPGA clock tree and you have the proper create_generated_clock constraint for the slow clock, then timing analysis results should be much improved.  

-then, we can talk about your need to “send data to an external 8-bit clocked register”.

Cheers,
Mark

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4 Replies
Highlighted
Scholar
Scholar
355 Views
Registered: ‎05-21-2015

Re: Timing problems at low clock

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Most FPGA tools can't handle clocks generated in logic like that.  Vivado is no different.  You might be able to cheat by placing your clock on a global buffer input--but you'd still need to find a way to tell Vivado what speed your "clock" (which isn't a clock) is running at.

Here's another approach to consider.

Dan

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Highlighted
Visitor
Visitor
328 Views
Registered: ‎12-25-2019

Re: Timing problems at low clock

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Vivado has create_generated_clock for this pourpose. Is not my case?

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Highlighted
265 Views
Registered: ‎01-22-2015

Re: Timing problems at low clock

Jump to solution

@thieulam 

Welcome!  

Lots of things in your post for us to discuss.

First, your VHDL low_clk is not a clock.  Even though it looks like a clock, it is only a VHDL signal because it has not been placed in the FPGA clock tree.  -and your create_generated_clock constraint for low_clk needs fixing.

A good way to generate a slow clock is to route a fast clock through a clock buffer (eg. BUFGCE) that has a clock enable, CE, pin.  Then, by properly toggling CE, you can create a slow clock that is in the FPGA clock tree.  This method is described by Avrum in <this> post.  

Next, the create_generated_clock constraint for the slow clock is described by Avrum in <this> post.  

Once your slow clock is placed in the FPGA clock tree and you have the proper create_generated_clock constraint for the slow clock, then timing analysis results should be much improved.  

-then, we can talk about your need to “send data to an external 8-bit clocked register”.

Cheers,
Mark

View solution in original post

Highlighted
Visitor
Visitor
243 Views
Registered: ‎12-25-2019

Re: Timing problems at low clock

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perfect thanks.
Now I will try the solution you recommended.

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