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venkat_vs2k2
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Registered: ‎11-19-2010

Timing problems when routing top level hdl ports externally on Microblaze

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Hello all

 

Could some one please help me with the issue I am having. ? Does routing the signal externally, i.e. on EDK , via system assembly  have a direct impact on timing ? I am not sure what is going wrong. Here is my problem,. 

 

 

I have designed an avionic serial communication protocol . I am testing the system on a ML605 board , instantiating my design as a PLBv46 Slave peripheral. 
 
-- About the Design 
 
 The design consists of two modules namely, Remote Terminal (RT) and Bus Controller (BC) . Each module has differential pair 2 Transmit and 2 Receive channels through which they exchange command and data.  i.e 
 
TxA_BC TXAn_BC TxB_BC   TXBn_BC   RxA_BC RxAn_BC, RxB_BC, RxBn_BC (all of the above are std_logic type)
 
Similarly 
 
TxA_RT TXAn_RT TxB_RT TXBn_RT RxA_RT RxAn_RT, RxB_RT, RxBn_RT  (all of the above are std_logic type)
 
The entire system is synchronous . 
 
-- Interfacing with the Microblaze
 
 
The design's top level module has been instantiated as a Microblaze peripheral device. The top level module of the design was instantiated inside the userlogic.vhd
 
 
--- Checking with Internal loopback using signal buffers
 
In order to check if the system is working properly, I did a loop back as follows  using internal signals declared. Then, the system works perfectly fine. 
 
signalTxA_BC :  std_logic ;
 signalTxAn_BC :  std_logic ;
 signalTxB_BC :  std_logic ;
 signalTxBn_BC :  std_logic ;
 signalRxA_BC :  std_logic ;
 signalRxAn_BC :  std_logic ;
 signalRxB_BC :  std_logic ;
 signalRxBn_BC :  std_logic ;
 
 signalTxA_RT :  std_logic ;
 signalTxAn_RT :  std_logic ;
 signalTxB_RT :  std_logic ;
 signalTxBn_RT :  std_logic ;
 signalRxA_RT :  std_logic ;
 signalRxAn_RT :  std_logic ;
 signalRxB_RT :  std_logic ;
 signalRxBn_RT :  std_logic ;
 
 IPCORE : IP1553_BC_RT_top
  port map
  (
  clock  => Bus2IP_Clk,
reset  => Bus2IP_Reset,
 
TxA_BC => TxA_BC,
TxAn_BC => TxAn_BC,
TxB_BC => TxB_BC,
TxBn_BC => TxBn_BC,
RxA_BC => TxA_RT,
RxAn_BC => TxAn_RT,
RxB_BC => TxB_RT,
RxBn_BC => TxBn_RT,
 
TxA_RT => TxA_RT,
TxAn_RT => TxAn_RT,
TxB_RT => TxB_RT,
TxBn_RT => TxBn_RT,
RxA_RT => TxA_BC,
RxAn_RT => TxAn_BC,
RxB_RT => TxB_BC,
RxBn_RT => TxBn_BC,
  );  
 
 
---- --- Checking w/o Internal loopback with microblaze peripheral external port 
 
When I route my signals via microblaze  EDK -- > System Assembly View -- > ports ,  without using internal loop back signals,  the design fails to work as expected. 
 
-- I am guessing the following possibilities 
 
1) Clock issues. Since, the signal goes inside a lot of sub-modules i.e. high fanout , there may be delay. But, however, the maximum post-PAR frequency of the design is 107 MHz and my clock is only 100 Mhz . and there are no timing errors on the EDK trce report.
 
2) External signals that are routed should go through a Global buffer / User constraints Should I use some kind of a global buffer to my top level I/O signals so that it is driven properly with user constraints ? 
 
 
Could you please help me on this issue and point me to mistake I am making here?  Otherwise, I cannot see why a properly functioning system (using internal signal loop-back) will not function when routed as Microblaze external ports 
 
Thank You, 

 Venkat

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venkat_vs2k2
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Registered: ‎11-19-2010

Hello Amandaw, 

 

Thank you for the reply! . Finally , I made it work .! :) Well turns out the problem was not on my part at all.  

 

So, untill up now I had been using EDK to synthesize,  PAR my design and used SDK to program the FPGA and test it in SW. 

 

Inorder to test my timing i wanted to used SmartXplorer . But inorder to do this, I had to use my EDK project in an ISE design flow. When I started to migrate my project to ISE and implemented the design,, something STRANGE happend . ! 

 

Design worked everytime !! Infact, it worked with the FMC loopback as well. :)  FINALLY!   :)
 
The problem seems to be with EDK . Not with the timing or design .  I checked the fully working design synthesizing it with both ISE and EDK
 
Not sure, why EDK causes this problem.. The design never works with EDK !!! 13.3 .  I see IOB being placed in both EDK as well as ISE. 
 
However, the design works with ISE , but not with EDK . I think It would be nice if Xilinx could make sure that this issue is not present in the future versions . 
 
Thank you for your replies. 
 
 
Cheers, 
 
Venkat 
 
PS:  I just explained it the full story just in case anyone else is/will be stuck up in a similar problem as mine. :)

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gszakacs
Professor
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Registered: ‎08-14-2007

I'm not quite clear on how you're testing the design when it fails.  Are you exernally

looping  the Rx and Tx pins at the board level?  If that's the case, then your PERIOD

time constraint does not cover the external path (clock to pad out --> pad in setup to clock).

You would need to also have OFFSET OUT AFTER constraints and OFFSET IN BEFORE

constraints on your transmit and receive signals respectively.  It would also help to

push the registers into the IOB's, which would force the best possible I/O timing.

Note that if you don't place I/O registers in the IOB, and only have a PERIOD constraint,

the tools may place these registers in the fabric with a large routing delay to the pad,

because that path is not covered by constraints, but placing the register near other

internal logic helps to meet the PERIOD constraint.

 

-- Gabor

-- Gabor
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venkat_vs2k2
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Hello Gszakacs,

 

Thanks a lot for your reply .  I am not doing anything at the board level now. I guess by board level you meat loop-back using an external wire ?  If my understanding was correct.  Although this would be my end goal.. In the end, I would want to use the protocol with an FMC module, where , i would be connecting two FMCs with Wires and testing the protocol.   

 

However, as of now, I am only doing a loopback at the EDK module level using the MHs file.  I try loopback using two methods, but both the methods doesn't seem to work. See the attached screenshots for both the types of loopback I am trying. 

However, the design works perfectly fine when i loopback using Signals declared in vhdl . checking the PAR frequency in EDK which is arnd 110 Mhz and i have a 100 Mhz clock . 

 

lpback_fig1 and lpback_fig2 shows a loopback where I declare an external signal as type IO and connect the Tx and Rx channels via the IO signal type on the system assembly view which is reflected in the MHs file. 

 

in the lpback_fig3 shows a loopback where i directly connect the Tx channel to the Rx channel via the system assembly view. 

 

Corresponding mhs of lpback_fig1 and lpback_fig2 

 

 PORT ip1553_0_TxA_BC = ip1553_0_TxA_BC, DIR = IO
 PORT ip1553_0_TxAn_BC = ip1553_0_TxAn_BC, DIR = IO
 PORT ip1553_0_TxB_BC = ip1553_0_TxB_BC, DIR = IO
 PORT ip1553_0_TxBn_BC = ip1553_0_TxBn_BC, DIR = IO
 PORT ip1553_0_TxA_RT = ip1553_0_TxA_RT, DIR = IO
 PORT ip1553_0_TxAn_RT = ip1553_0_TxAn_RT, DIR = IO
 PORT ip1553_0_TxB_RT = ip1553_0_TxB_RT, DIR = IO
 PORT ip1553_0_TxBn_RT = ip1553_0_TxBn_RT, DIR = IO


BEGIN ip1553
 PARAMETER INSTANCE = ip1553_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xcde00000
 PARAMETER C_HIGHADDR = 0xcde0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT TxA_BC = ip1553_0_TxA_BC
 PORT TxAn_BC = ip1553_0_TxAn_BC
 PORT TxB_BC = ip1553_0_TxB_BC
 PORT TxBn_BC = ip1553_0_TxBn_BC
 PORT TxA_RT = ip1553_0_TxA_RT
 PORT TxAn_RT = ip1553_0_TxAn_RT
 PORT TxB_RT = ip1553_0_TxB_RT
 PORT TxBn_RT = ip1553_0_TxBn_RT
 PORT RxA_RT = ip1553_0_TxA_BC
 PORT RxAn_RT = ip1553_0_TxAn_BC
 PORT RxB_RT = ip1553_0_TxB_BC
 PORT RxBn_RT = ip1553_0_TxBn_BC
 PORT RxA_BC = ip1553_0_TxA_RT
 PORT RxAn_BC = ip1553_0_TxAn_RT
 PORT RxB_BC = ip1553_0_TxB_RT
 PORT RxBn_BC = ip1553_0_TxBn_RT
END

 

Corresponding mhs of lpback_fig3

 

 

BEGIN ip1553
 PARAMETER INSTANCE = ip1553_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xcde00000
 PARAMETER C_HIGHADDR = 0xcde0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT TxA_BC = ip1553_0_TxA_BC
 PORT RxA_RT = ip1553_0_TxA_BC
 PORT TxAn_BC = ip1553_0_TxAn_BC
 PORT RxAn_RT = ip1553_0_TxAn_BC
 PORT TxB_BC = ip1553_0_TxB_BC
 PORT RxB_RT = ip1553_0_TxB_BC
 PORT TxBn_BC = ip1553_0_TxBn_BC
 PORT RxBn_RT = ip1553_0_TxBn_BC
 PORT TxA_RT = ip1553_0_TxA_RT
 PORT RxA_BC = ip1553_0_TxA_RT
 PORT RxAEnb_BC = ip1553_0_RxAEnb_BC
 PORT RxAn_BC = ip1553_0_TxAn_RT
 PORT TxAn_RT = ip1553_0_TxAn_RT
 PORT TxB_RT = ip1553_0_TxB_RT
 PORT RxB_BC = ip1553_0_TxB_RT
 PORT TxBn_RT = ip1553_0_TxBn_RT
 PORT RxBn_BC = ip1553_0_TxBn_RT
END

 

 

 

Thanks

lpback_fig1.JPG
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venkat_vs2k2
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lpback_fig2.jpg
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venkat_vs2k2
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lpback_fig3.JPG
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venkat_vs2k2
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Hello Gabor, 

 

Could you please give me some more pointers on this. 

 
I am trying to use the OFFSET IN and OFFSET OUT constraints to solve the issue  (if timing is the problem in this case). As, I do not find any other suitable constraints for I/O ports for this particular case . 
 
However, I am running into the following problems
-- I do not use any top level clock signals/pins directly in my design. Since my design is a PLB slave, it uses the PLB slave clock from the PLB tree. 
-- So should I apply the constraint to the Global clock pin in this case (200 MHz) or the clock_generator (DCM output) which is 100Mhz that serves as the clock signal to the entire system ? 
-- How do I calculate the path delay in the external path in order to apply the global OFFSET IN/OUTconstraint ? 
 
also I assume the systesis tools adds I/o buffers to the ports automatically , because, I have "checked" the "iobuf" in the process properties.  
 
 
Any other comments / suggestions much appreciated.  Sorry if the questions sound like noob, but timing analysis and constraints are quite new to me. 
 
 
Thank you, 
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amandaw
Xilinx Employee
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Registered: ‎02-02-2010

It seems like you're having trouble because you're declaring an external signal where there isn't one.  If you're not pulsing on some kind of external access, I'm not sure how you could test TX or RX functionality.  If your eventual goal is to implement external hardware looping via FMC, the XM105 Debug Daughter Card provides external headers for FMC that would be easy to play with.

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venkat_vs2k2
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Registered: ‎11-19-2010

Hello Amandaw, 

 

Thank you for the reply! . Finally , I made it work .! :) Well turns out the problem was not on my part at all.  

 

So, untill up now I had been using EDK to synthesize,  PAR my design and used SDK to program the FPGA and test it in SW. 

 

Inorder to test my timing i wanted to used SmartXplorer . But inorder to do this, I had to use my EDK project in an ISE design flow. When I started to migrate my project to ISE and implemented the design,, something STRANGE happend . ! 

 

Design worked everytime !! Infact, it worked with the FMC loopback as well. :)  FINALLY!   :)
 
The problem seems to be with EDK . Not with the timing or design .  I checked the fully working design synthesizing it with both ISE and EDK
 
Not sure, why EDK causes this problem.. The design never works with EDK !!! 13.3 .  I see IOB being placed in both EDK as well as ISE. 
 
However, the design works with ISE , but not with EDK . I think It would be nice if Xilinx could make sure that this issue is not present in the future versions . 
 
Thank you for your replies. 
 
 
Cheers, 
 
Venkat 
 
PS:  I just explained it the full story just in case anyone else is/will be stuck up in a similar problem as mine. :)

View solution in original post

gszakacs
Professor
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Registered: ‎08-14-2007

If you would like this solved for future versions of EDK, I would suggest opening a webcase.

Posting a problem on the forums does not guarantee notice by those involved in updating

the software tool chain.

 

-- Gabor

-- Gabor
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venkat_vs2k2
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Done! 

 

 

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