Timing synchronization reset

[sarit8]

I have a block named "rx_top" which contains block named rx_fe_srstn_sm which has output named srstn_out which is the input for another block in rx_top named rx_fe.

rx__top gets 250_clk where rx_fe gets two input clocks - 125_clk and 250_clk.

rx_fe contain block named dc_and_pow_est which gets as inputs srstn, and 125_clk.

dc_and_pow_est contain ar1_avg_pow which also gets as inputs srstn, and 125_clk.

Block diagram file is attached (srstn. PNG)

I have timing issue with srstn - a file is attached.

I assume that there is a timing synchronization reset....

Is there anyway to fix it except multi cycle path?

[embedded]

From error messages it seems that reset signal is not synchronized and constrained well enough. Below are some questions:

• Where has the mentioned reset synchronizer been placed? inside rx_fe_srstn_out module or dc_and_pow_est ?
• What is the clock for synchronizer?! You should use that 125_clk for synchronizing reset!.

You have to synchronize the input reset with 125_clk by Async assertion and Synchronous de-assertion. Do use ASYNC_REG attribute in your VHDL/Verilog code or place it in your XDC file.

Besides, to cover the maximum delay for the reset inputs of rx_fe module you can add set_max_delay on the output signal of your synchronizing circuitry.

Hope this would help,

Hossein

[sarit8]

 The reset synchronizer has been placed outside/before rx_top.

I attached the file of the reset synchronizer.

[sarit8]

I have tried to use the following multicycle path:

set_multicycle_path -setup -from [get_pins {rx_top_i/rx_fe_srstn_sm/srstn_out_reg/C}] -to [get_pins {rx_top_i/rx_fe_i/dc_and_pow_est_i/ar1_avg_pow_i/y_n_m1_int_reg[*]/D}] 2
set_multicycle_path -hold -from [get_pins {rx_top_i/rx_fe_srstn_sm/srstn_out_reg/C}] -to [get_pins {rx_top_i/rx_fe_i/dc_and_pow_est_i/ar1_avg_pow_i/y_n_m1_int_reg[*]/D}] 1

But I still get the time's error....

[embedded]

This is not so clear for me which kind of synchronizer that circuit is?

Shouldn't it have a clock ?! 

Besideds, are you using it as a reset for 125_clk DCM? 

You should use that 125_clk clock for your synchronizer. And, this shouldn't be used as a DCM reset of module which generates 125_clk?!

Hope this would whelp,

Hossein 

[sarit8]

This is the code for the synchronizer:

entity srstn_chan_idx is
  port(
    clk       : in  std_logic;
    clk_div2  : in  std_logic;
    arstn     : in  std_logic;
    srstn_out : out std_logic;
    clk_en2   : in  std_logic;
    chind2    : out integer range 0 to 1
    );

-- Declarations

end srstn_chan_idx;


architecture behave of srstn_chan_idx is

  signal chind2_cnt : integer range 0 to 1;
  signal srstn_int  : std_logic;
  signal clk_en2_b  : std_logic_vector(0 downto 0);
  
begin

  srstn_out    <= srstn_int;
  clk_en2_b(0) <= not(clk_en2);

  chind2_proc : process (clk, arstn)
  begin  -- process chind2_proc
    if arstn = '0' then                 -- asynchronous reset (active low)
      chind2 <= 0;
    elsif clk'event and clk = '1' then  -- rising clock edge
      chind2 <= conv_integer(unsigned(clk_en2_b));
    end if;
  end process chind2_proc;

  srstn_proc : process (clk_div2, arstn)
  begin  -- process srstn_proc
    if arstn = '0' then                 -- asynchronous reset (active low)
      srstn_int <= '0';
    elsif clk_div2'event and clk_div2 = '1' then  -- rising clock edge
      srstn_int <= '1';
    end if;
  end process srstn_proc;

end architecture behave;

Where the input for clk is is 250_clk and for clk_div2 (clk_div2  is missing  in the scheme - my mistake)

[embedded]

If you are going to synchronize an asynchronous reset - like a push button in your board - You should obviously use double flopping and also - as I mentioned earlier -  use asynchronous assertion and synchronous de-assertion. I doubt if the attached code is working properly.

Simple Synchronizer code is as below:

entity RstSync is
 port(
   iExtRst     : in std_logic;
   iClk        : in std_logic;
   oSyncRst    : out std_logic
);

end RstSync;

architecture bhv of RstSync is
signal sRst0 : std_logic:='0';
signal sRst1 : std_logic:='0';

attribute ASYNC_REG : string;
attribute ASYNC_REG of sRst0      : signal is "TRUE";
attribute ASYNC_REG of sRst1      : signal is "TRUE";
begin

 process(iExtRst ,iCLK)
 begin
  if iExtRst ='0' then
   sRst0 <= '1';
   sRst1 <= '1';
   oSyncRst <= '1';
  elsif rising_edge(iClk) then
   sRst0 <= '0';
   sRst1 <= sRst0;
   oSyncRst  <= sRst1;
  end if;
 end process;

end bhv;

ASYNC_REG attribute will help placer use the same SLICE for these two FFs to shorten delay time between flip flops.

Hope this will help,

Hossein

[avrumw]

Take a look at this forum post on a reset bridge.

Avrum