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Anonymous
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Timing violation of SLR crossing and hold time issue

I have two timimg issue,

(a) how to solve SLR crossing as large clock path skew as below,

 

Slack (VIOLATED) :        -3.379ns  (required time - arrival time)
  Source:                 i08_rfb_top/u_fifo_od_sync_o/po_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by pll_h  {rise@0.000ns fall@3.350ns period=6.700ns})
  Destination:            i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]/D
                            (rising edge-triggered cell FDCE clocked by pll_h  {rise@0.000ns fall@3.350ns period=6.700ns})
  Path Group:             pll_h
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.700ns
  Data Path Delay:        7.259ns  (logic 0.534ns (7.357%)  route 6.725ns (92.643%))
  Logic Levels:           5  (LUT2=1 LUT4=1 LUT6=3)
  Clock Path Skew:        -2.394ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.768ns = ( 11.468 - 6.700 )
    Source Clock Delay      (SCD):    7.492ns
    Clock Pessimism Removal (CPR):    0.330ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Inter-SLR Compensation: 0.426ns
 
    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pll_h rise edge)      0.000     0.000 r
    H19                                                       0.000     0.000 r  DIFF_CLK_P_A
                         net (fo=0)                         0.000     0.000    i01_analog_top/DIFF_CLK_P_A
    H19                                                                                        r  i01_analog_top/uIBUFDS_pll_h/I
    H19      IBUFDS (Prop_ibufds_I_O)     1.043     1.043 r  i01_analog_top/uIBUFDS_pll_h/O
             net (fo=14931, routed)                 6.449     7.492    i08_rfb_top/u_fifo_od_sync_o/clk_shr_src
    SLR Crossing[2->1]
    SLICE_X175Y251                                                    r  i08_rfb_top/u_fifo_od_sync_o/po_reg[0]/C
  -------------------------------------------------------------------    -------------------
    (N)SLICE_X175Y251    FDCE (Prop_fdce_C_Q)         0.269     7.761 r  i08_rfb_top/u_fifo_od_sync_o/po_reg[0]/Q
                                                   net (fo=1, routed)           2.378    10.139    i08_rfb_top/u_reg_rfb/I1159[0]
    (N)SLICE_X175Y251                                                                             r  i08_rfb_top/u_reg_rfb/data_out_reg[30]_i_1/I3
    (N)SLICE_X175Y251    LUT6 (Prop_lut6_I3_O)          0.053    10.192 r  i08_rfb_top/u_reg_rfb/data_out_reg[30]_i_1/O
                                                  net (fo=5, routed)            1.120    11.312    i08_rfb_top/u_reg_rfb/O620
    (N)SLICE_X201Y276                                                                            r  i08_rfb_top/u_reg_rfb/rd_pixel_cnt_reg[5]_i_3/I0
    (N)SLICE_X201Y276    LUT2 (Prop_lut2_I0_O)        0.053    11.365 r  i08_rfb_top/u_reg_rfb/rd_pixel_cnt_reg[5]_i_3/O
                         net (fo=14, routed)                                 0.603    11.968    i08_rfb_top/u_mcore/u0_psr_oif/p_1_out__0
    (N)SLICE_X205Y283                                                                      r  i08_rfb_top/u_mcore/u0_psr_oif/rd_pixel_cnt_reg[5]_i_10/I3
    (N)SLICE_X205Y283    LUT4 (Prop_lut4_I3_O)        0.053    12.021 r  i08_rfb_top/u_mcore/u0_psr_oif/rd_pixel_cnt_reg[5]_i_10/O
                                                net (fo=20, routed)          1.914    13.935    i08_rfb_top/u_mcore/u0_psr_oif/p_20_out
    SLR Crossing[1->2]
    (N)SLICE_X204Y343                                                 r  i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]_i_2/I5
    (N)SLICE_X204Y343    LUT6 (Prop_lut6_I5_O)        0.053    13.988 r  i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]_i_2/O
                                                 net (fo=1, routed)           0.710    14.698    i08_rfb_top/u_mcore/u0_psr_oif/n_1_data_out_reg[17]_i_2
    (N)SLICE_X204Y340                                                                         r  i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]_i_1/I0
    (N)SLICE_X204Y340    LUT6 (Prop_lut6_I0_O)        0.053    14.751 r  i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]_i_1/O
                                                 net (fo=1, routed)           0.000    14.751    i08_rfb_top/u_mcore/u0_psr_oif/n_1_data_out_reg[17]_i_1
    (N)SLICE_X204Y340                                                 r  i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]/D
  -------------------------------------------------------------------    -------------------
 

                         (clock pll_h rise edge)      6.700     6.700 r
    H19                                                        0.000     6.700 r  DIFF_CLK_P_A
                                net (fo=0)                   0.000     6.700    i01_analog_top/DIFF_CLK_P_A
    H19                                                               r  i01_analog_top/uIBUFDS_pll_h/I
    H19                 IBUFDS (Prop_ibufds_I_O)     0.925     7.625 r  i01_analog_top/uIBUFDS_pll_h/O
                                 net (fo=14931, routed)       3.843    11.468    i08_rfb_top/u_mcore/u0_psr_oif/clk_shr_src
    SLICE_X204Y340                                                               r  i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]/C
                                   clock pessimism              0.330    11.798
                             inter-SLR compensation      -0.426    11.372
                                    clock uncertainty           -0.035    11.337
    (N)SLICE_X204Y340    FDCE (Setup_fdce_C_D)        0.035    11.372    i08_rfb_top/u_mcore/u0_psr_oif/data_out_reg[17]
  -------------------------------------------------------------------
                         required time                         11.372
                         arrival time                         -14.751
  -------------------------------------------------------------------
                         slack                                 -3.379
 
 
(b) Hold time fix : At vivado, I added -hold_fix for phys_opt_design, but still have the hold time issue. Normally, whether the hold time will be fix by vivado ? How can I do next as below report,
Slack (VIOLATED) :        -0.745ns  (arrival time - required time)
  Source:                 i11_backend_main/u01_de_gen/valdet_vact_u1/vact_cnt_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by pll_h  {rise@0.000ns fall@3.350ns period=6.700ns})
  Destination:            i11_backend_main/u01_de_gen/valdet_vact_u1/vact_val_pre_reg[10]/D
                            (rising edge-triggered cell FDCE clocked by pll_h  {rise@0.000ns fall@3.350ns period=6.700ns})
  Path Group:             pll_h
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns
  Data Path Delay:        0.595ns  (logic 0.216ns (36.284%)  route 0.379ns (63.716%))
  Logic Levels:           0
  Clock Path Skew:        1.171ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.634ns
    Source Clock Delay      (SCD):    6.812ns
    Clock Pessimism Removal (CPR):    0.651ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pll_h rise edge)      0.000     0.000 r
    H19                                                       0.000     0.000 r  DIFF_CLK_P_A
                         net (fo=0)                          0.000     0.000    i01_analog_top/DIFF_CLK_P_A
    H19                                                                                   r  i01_analog_top/uIBUFDS_pll_h/I
    H19      IBUFDS (Prop_ibufds_I_O)     0.925     0.925 r  i01_analog_top/uIBUFDS_pll_h/O
                       net (fo=14931, routed)       5.887     6.812    i11_backend_main/u01_de_gen/valdet_vact_u1/clk_shr
    SLR Crossing[2->1]
    SLICE_X56Y222                                                     r  i11_backend_main/u01_de_gen/valdet_vact_u1/vact_cnt_reg[10]/C
  -------------------------------------------------------------------    -------------------
    (N)SLICE_X56Y222     FDCE (Prop_fdce_C_Q)      0.216     7.028 r i11_backend_main/u01_de_gen/valdet_vact_u1/vact_cnt_reg[10]/Q
                                                net (fo=5, routed)           0.379     7.407    i11_backend_main/u01_de_gen/valdet_vact_u1/n_1_vact_cnt_reg[10]
    (N)SLICE_X56Y223                                                  r  i11_backend_main/u01_de_gen/valdet_vact_u1/vact_val_pre_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock pll_h rise edge)      0.000     0.000 r
    H19                                                       0.000     0.000 r  DIFF_CLK_P_A
                         net (fo=0)                         0.000     0.000    i01_analog_top/DIFF_CLK_P_A
    H19                                                                                r  i01_analog_top/uIBUFDS_pll_h/I
    H19      IBUFDS (Prop_ibufds_I_O)     1.043     1.043 r  i01_analog_top/uIBUFDS_pll_h/O
                       net (fo=14931, routed)       7.591     8.634    i11_backend_main/u01_de_gen/valdet_vact_u1/clk_shr
    SLR Crossing[2->1]
    SLICE_X56Y223                                                     r  i11_backend_main/u01_de_gen/valdet_vact_u1/vact_val_pre_reg[10]/C
                         clock pessimism             -0.651     7.983
    (N)SLICE_X56Y223     FDCE (Hold_fdce_C_D)         0.169     8.152    i11_backend_main/u01_de_gen/valdet_vact_u1/vact_val_pre_reg[10]
  -------------------------------------------------------------------
                         required time                         -8.152
                         arrival time                           7.407
  -------------------------------------------------------------------
                         slack                                 -0.745
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4 Replies
htsvn
Xilinx Employee
Xilinx Employee
12,867 Views
Registered: ‎08-02-2007

Hi,

 

Do try the following suggestions:-

 

Step1: Let the tool run through the design once without any pblocks and check how the placement looks in the post-placed design.

Step 2: Create pblock for each of the SLR based on the Vivado placed design.

Step 3: Run through the implementation and check if timing violation paths are SLR crossings. If the start and end points are far from the SLR boundaries, try using another pblock to confine the problematic blocks closer to SLR boundaries.

 

--Hem

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driesd
Xilinx Employee
Xilinx Employee
12,861 Views
Registered: ‎11-28-2007

Hi Kelvin,

 

- for your reference -

we have some very good documentation on working with these stacked silicon devices:

UG872 - Large FPGA Methodology Guide

 

There is also a short section in UG906 - Vivado Design Analysis and Closure Techniques, showing what Hemasunder was explaining:

screenshot_001.jpg

 

 

Best regards

Dries

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avrumw
Guide
Guide
12,859 Views
Registered: ‎01-23-2009

By looking at the failing timing path, the problem is fairly obvious...

 

You have not buffered your clock!

 

The clock comes directly from an IBUFDS input and goes to the clock pin of some flip-flops. Since no clock buffer is used, the clock is routed in fabric logic. This is always a formula for disaster. This is compounded by the fact that the source and destination flip-flops appear to be in different SLRs.

 

You need to buffer your clock using a clock buffer - probably a BUFG.

 

Avrum

driesd
Xilinx Employee
Xilinx Employee
12,856 Views
Registered: ‎11-28-2007


@avrumw wrote:

By looking at the failing timing path, the problem is fairly obvious...

 

You have not buffered your clock!

 

The clock comes directly from an IBUFDS input and goes to the clock pin of some flip-flops. Since no clock buffer is used, the clock is routed in fabric logic. This is always a formula for disaster. This is compounded by the fact that the source and destination flip-flops appear to be in different SLRs.

 

You need to buffer your clock using a clock buffer - probably a BUFG.

 

Avrum


good catch Avrum!

 

Looking for one of the most advanced problems...

Missing one of the most basic principles!

 

It probably won't solve everything, but it will definitely help A LOT!

 

 

- Dries

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