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Observer
Observer
7,162 Views
Registered: ‎01-29-2009

Timing warning when running par

Hi all,

 

I get the message below when running the place and route in a Spartan3-ADSP device

 

Thanks in advance

 

Andoni

 

========================================================================

 

Release 10.1.03 par K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

MOORE::  Wed Nov 19 22:22:08 2008

par -ol high -w ./work/fpga_cf_dn_rb_wg_ac_pf.ncd
./work/fpga_cf_dn_rb_wg_ac_pf_pr.ncd ./work/fpga_cf_dn_rb_wg_ac_pf.pcf


Constraints file: ./work/fpga_cf_dn_rb_wg_ac_pf.pcf.
Loading device for application Rf_Device from file '3sd1800a.nph' in environment C:\Xilinx\10.1\ISE.
   "fpga_cf_dn_rb_wg_ac_pf" is an NCD, version 3.2, device xc3sd1800a, package cs484, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:3232 - Timing Constraint
   "TS_CLK_140 = PERIOD TIMEGRP "clk_140" 7.1 ns HIGH 3.55 ns;"
    fails the minimum period check for clock "clk_140" because the period constraint value (7100 ps) is less than the
   minimum internal period limit of 7350 ps  on pin
   "/fpga_cf_dn_rb_wg_ac_pf/PACKED/fpga_cf_dn_rb_wg_ac_pf/dn\/u2\/Mmult_dgain_mult0000/dn\/u2\/Mmult_dgain_mult0000/CLK"
   .   Please increase the period of the constraint to remove this timing failure.
WARNING:Timing:3232 - Timing Constraint
   "TS_dcm1_CLK0_BUF = PERIOD TIMEGRP "dcm1_CLK0_BUF" TS_clk HIGH 50%;"
    fails the minimum period check for clock "clk_140" because the period constraint value (7100 ps) is less than the
   minimum internal period limit of 7350 ps  on pin
   "/fpga_cf_dn_rb_wg_ac_pf/PACKED/fpga_cf_dn_rb_wg_ac_pf/dn\/u2\/Mmult_dgain_mult0000/dn\/u2\/Mmult_dgain_mult0000/CLK"
   .   Please increase the period of the constraint to remove this timing failure.

 

============================================================================================

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3 Replies
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Participant
Participant
7,116 Views
Registered: ‎05-12-2008

Re: Timing warning when running par

Hello,

This message warn you that the clock frequency is beyond the requirement of that INST (it seems to be a DSP48A) due to input clock period constraint.

Please double chech the spartan3ADSP's datasheet.

 

Regards,

Jared

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Anonymous
Not applicable
6,975 Views

Re: Timing warning when running par

Those warnings are for DCM pin limit check.

Which clock output has it gone out from the DCM? Which mode is the DCM working under? 

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Observer
Observer
6,967 Views
Registered: ‎01-29-2009

Re: Timing warning when running par

The one that it producing the warning is the CLK0 output.

The DCM mode is a single DCM that produces two outputs, one is of the same frequency as the input and other which is half its frequency.

 

Regards

 

Andoni

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