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Visitor fpga.deve
Visitor
11,470 Views
Registered: ‎10-13-2014

Timming and power reports error

Some strange numbers in timming report. Delays with billions of ns.

1.png

 

 

2.png

 

I can't understand what is the reason of this

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8 Replies
Xilinx Employee
Xilinx Employee
11,454 Views
Registered: ‎04-16-2012

Re: Timming and power reports error

Hello,

 

Which version of Vivado are you using?

Can you check with latest Vivado 2014.3 tool?

 

Thanks,

Vinay

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Visitor fpga.deve
Visitor
11,441 Views
Registered: ‎10-13-2014

Re: Timming and power reports error

I am using Vivado 2014.3. Same issue was in the 2014.2.

Operating system is Ubuntu 14.04 LTS 64 bit.

 

Issue looks similar to this:

http://forums.xilinx.com/t5/Synthesis/Vivado-timing-reports-Billion-ns-data-path-delay-on-DSP48-for/td-p/391467

 

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Teacher muzaffer
Teacher
11,393 Views
Registered: ‎03-31-2012

Re: Timming and power reports error

Try setting output delay on your IOs. Somehow there is a 1 second delay on your outputs which is causing the problem.
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Xilinx Employee
Xilinx Employee
11,386 Views
Registered: ‎07-16-2008

Re: Timming and power reports error

Moving to Timing board.

 

I see the attached result is in synthesized design. What about implemented design? Is the same abnormal logic delay observed?

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Moderator
Moderator
11,377 Views
Registered: ‎01-16-2013

Re: Timming and power reports error

Share your XDC file and report file.
If possible share complete test case.

Thanks,
Yash
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Visitor fpga.deve
Visitor
11,249 Views
Registered: ‎10-13-2014

Re: Timming and power reports error

The  issue was on Linux hosts (Ubuntu 32 and 64 bits). Same timming and power problems was in Vivado example projects.

 

I have tried same steps in Vivado installed on Windows 7 host and there are no issues with timming and power analysis.

 

Think the problem may be in Ubuntu regional formats(comma or dot used in decimal numbers).

 

My XDC:

create_clock -period 10.000 -name c -waveform {0.000 5.000} -add [get_ports c]
set_input_delay -clock [get_clocks c] -min -add_delay 1.000 [get_ports d]
set_input_delay -clock [get_clocks c] -max -add_delay 2.000 [get_ports d]
set_output_delay -clock [get_clocks c] -min -add_delay 1.000 [get_ports q]
set_output_delay -clock [get_clocks c] -max -add_delay 2.000 [get_ports q]
set_output_delay -clock [get_clocks c] -min -add_delay 1.000 [get_ports q1]
set_output_delay -clock [get_clocks c] -max -add_delay 2.000 [get_ports q1]

 

Thanks

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Moderator
Moderator
11,176 Views
Registered: ‎01-16-2013

Re: Timming and power reports error

hi,

your XDC constraints looks fine to me.
Are you facing any warning or something in ubuntu?

This looks like OS specific issue. Have you checked the checksum value of vivado install before installing it on your ubuntu environment?

If you have multiple ubuntu machine can you try with some other ubuntu machine?

It will help to narrow down this issue,

Thanks,
Yash
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Visitor fpga.deve
Visitor
11,152 Views
Registered: ‎10-13-2014

Re: Timming and power reports error

Hello,

 

The issue is Ubuntu Regional Formats setting.

Switch to other format helped. So most probably problem is in decimal mark because it can be dot or comma. May be Vivado can work only if dot is used to separate fractional part. I think problem is parsing decimal numbers.

 

Thanks

 

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