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jonmccallum
Participant
Participant
8,975 Views
Registered: ‎12-10-2013

Tool Clock Grouping Error

Hello All,

 

I am taking a synthesized netlist from synplify_pro and trying to run implementation on it.

 

When I am running synplify_pro I am using the -use_vivado option which creates the clock generated .xdc constraints file that is needed for vivado to run implementation.

 

When ever I run implementaion and read in this file there is a particular bug that I keep runnign into.

 

The best Way to Describe it is with examples.

 

EXAMPLE 1 Working Constraints File

################################
#     Create Clock Clocks
################################
create_clock -name {osc_clk}    [get_ports {pta[18]}]                                    -period {40.0}  -waveform {0 20.0}
create_clock -name {ref_clk}    [get_pins {clkgen/fpga_clk_gen_system/REF_CLK_BUF/O}]    -period {40.0}  -waveform {0 20.0}
create_clock -name {pll_clkfb}  [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKFBOUT}] -period {10.0}  -waveform {0 5.0}
create_clock -name {pll_flash}  [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT0}]  -period {10.0}  -waveform {0 5.0}
create_clock -name {pll_sample} [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT1}]  -period {20.0}  -waveform {0 10.0}
create_clock -name {pll_sys}    [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT2}]  -period {40.0}  -waveform {0 20.0}
create_clock -name {pll_bus}    [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT3}]  -period {80.0}  -waveform {0 40.0}
create_clock -name {pll_ir}     [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT4}]  -period {160.0} -waveform {0 80.0}

create_clock -name {real_clock}  [get_pins {srtc/srtc_compen_cnt[7]/C srtc/srtc_compen_cnt[6]/C srtc/srtc_compen_cnt[5]/C srtc/srtc_compen_cnt[4]/C srtc/srtc_compen_cnt[3]/C srtc/srtc_compen_cnt[2]/C srtc/srtc_compen_cnt[1]/C srtc/srtc_compen_cnt[0]/C srtc/srtc_compensation_0[0]/C srtc/ipi_int_srtc_1hz_async/C srtc/srtc_compensation[2]/C srtc/srtc_compensation[1]/C srtc/srtc_compensation[7]/C srtc/srtc_compensation[6]/C srtc/srtc_compensation[5]/C srtc/srtc_compensation[4]/C srtc/srtc_compensation[3]/C srtc/srtc_time_alarm/C srtc/srtc_seconds/srtc_time_overflow/C srtc/srtc_seconds/srtc_ripplecnt/COUNTER_LP.srtc_ripplereg/RIPPLE_REG[0].dataout[0]/C srtc/srtc_seconds/srtc_ripplecnt/COUNTER_LP.srtc_ripplereg/RIPPLE_REG[0].dataout_125/C}] -period {1000.0}  -waveform {0 500.0} 

create_clock -name {ident_coreinst.comm_block_INST.tck}        [ get_pins {ident_coreinst_comm_block_INST/jtagi_clkbuf/O}]          -period {40}  -waveform {0 20.0}
create_clock -name {ident_coreinst.comm_block_INST.dr2_tck}    [ get_pins {ident_coreinst_comm_block_INST/jtagi_clkbuf2/O}]         -period {40}  -waveform {0 20.0}
create_clock -name {ident_coreinst.comm_block_INST.ch_update}  [ get_pins {ident_coreinst_comm_block_INST/jtagi_jtag_prim1/UPDATE}] -period {40}  -waveform {0 20.0}
create_clock -name {ident_coreinst.comm_block_INST.hcr_update} [ get_pins {ident_coreinst_comm_block_INST/jtagi_jtag_prim2/UPDATE}] -period {40}  -waveform {0 20.0}
create_clock -name {lsim_debug|fclk_div2_derived_clock}        [ get_nets lsim/lsim_debug/fclk_div2]                                -period {40}  -waveform {0 20.0}

create_generated_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}] -source [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/C}] -master_clock {osc_clk} -add -multiply_by 1

create_generated_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}] -source [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/C}] -master_clock {pll_ir} -add -multiply_by 1

create_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}]  -period {  80.000} -waveform {0.000 40.000}

create_generated_clock -name {rgpio2p_12s_5s_160s_31_0s_0s_1s_248_Z33|ipp_do_gpio_1_derived_clock[2]} [get_pins {rpp_dual_cm0p_l5k/rpp_dual_cm0p_plat/rgpio2p/ipp_do_gpio_1[2]/Q}] -source [get_pins {rpp_dual_cm0p_l5k/rpp_dual_cm0p_plat/rgpio2p/ipp_do_gpio_1[2]/C}] -multiply_by 1

create_generated_clock -name {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock} [ get_pins {iic1/iic_cpu_regs/state_ff_ret_3/Q}]       -source [ get_pins {iic1/iic_cpu_regs/state_ff_ret_3/C}] -multiply_by 1
create_generated_clock -name {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}    [ get_pins {lsim/lsim_test_entry/q_tstcfg_lden_ret/Q}] -source [ get_pins {lsim/lsim_test_entry/q_tstcfg_lden_ret/C}] -multiply_by 1

################################
#     Set Clock Groups
################################
set_clock_groups -asynchronous -name {REAL} -group [get_clocks {real_clock}]


set_clock_groups -asynchronous -name {OSC}  -group [get_clocks {osc_clk lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock ref_clk}]
create_generated_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}] -source [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/C}] -master_clock {osc_clk} -add -multiply_by 1
set_clock_groups -asynchronous -name {OSC}  -group [get_clocks {osc_clk lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock ref_clk}]


set_clock_groups -asynchronous -name {IRC}  -group [get_clocks {pll_ir lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1}]
create_generated_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}] -source [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/C}] -master_clock {pll_ir} -add -multiply_by 1
set_clock_groups -asynchronous -name {IRC}  -group [get_clocks {pll_ir lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1}]


set_clock_groups -asynchronous -name {SYS} -group  [get_clocks {pll_clkfb pll_flash pll_sample pll_sys lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock rgpio2p_12s_5s_160s_31_0s_0s_1s_248_Z33|ipp_do_gpio_1_derived_clock[2] lsim_debug|fclk_div2_derived_clock pll_bus lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}]

set_clock_groups -asynchronous -name {identify_jtag_group1} -group  [get_clocks {ident_coreinst.comm_block_INST.tck ident_coreinst.comm_block_INST.dr2_tck ident_coreinst.comm_block_INST.ch_update ident_coreinst.comm_block_INST.hcr_update}]


################################
#     Set Multicycle path
################################
set_false_path -rise_from  [get_clocks {ident_coreinst.comm_block_INST.ch_update}]
set_multicycle_path -setup -end -from  [get_clocks {lsim_debug|fclk_div2_derived_clock}]                            -to [get_clocks {lsim_debug|fclk_div2_derived_clock}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {lsim_debug|fclk_div2_derived_clock}]                            -to [get_clocks {lsim_debug|fclk_div2_derived_clock}] {1}
set_multicycle_path -setup -end -from  [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] -to [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] -to [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] {1}
set_multicycle_path -setup -end -from  [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}]      -to [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}]      -to [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}] {1}
set_multicycle_path -setup -end -from  [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}]         -to [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}]         -to [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}] {1}

 

 

 

EXAMPLE 2 THE NON WORKING CLOCK CONSTRAINTS FILE

################################
#     Create Clock Clocks
################################
create_clock -name {osc_clk}    [get_ports {pta[18]}]                                    -period {40.0}  -waveform {0 20.0}
create_clock -name {ref_clk}    [get_pins {clkgen/fpga_clk_gen_system/REF_CLK_BUF/O}]    -period {40.0}  -waveform {0 20.0}
create_clock -name {pll_clkfb}  [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKFBOUT}] -period {10.0}  -waveform {0 5.0}
create_clock -name {pll_flash}  [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT0}]  -period {10.0}  -waveform {0 5.0}
create_clock -name {pll_sample} [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT1}]  -period {20.0}  -waveform {0 10.0}
create_clock -name {pll_sys}    [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT2}]  -period {40.0}  -waveform {0 20.0}
create_clock -name {pll_bus}    [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT3}]  -period {80.0}  -waveform {0 40.0}
create_clock -name {pll_ir}     [get_pins {clkgen/fpga_clk_gen_system/sys_pll/CLKOUT4}]  -period {160.0} -waveform {0 80.0}

create_clock -name {real_clock}  [get_pins {srtc/srtc_compen_cnt[7]/C srtc/srtc_compen_cnt[6]/C srtc/srtc_compen_cnt[5]/C srtc/srtc_compen_cnt[4]/C srtc/srtc_compen_cnt[3]/C srtc/srtc_compen_cnt[2]/C srtc/srtc_compen_cnt[1]/C srtc/srtc_compen_cnt[0]/C srtc/srtc_compensation_0[0]/C srtc/ipi_int_srtc_1hz_async/C srtc/srtc_compensation[2]/C srtc/srtc_compensation[1]/C srtc/srtc_compensation[7]/C srtc/srtc_compensation[6]/C srtc/srtc_compensation[5]/C srtc/srtc_compensation[4]/C srtc/srtc_compensation[3]/C srtc/srtc_time_alarm/C srtc/srtc_seconds/srtc_time_overflow/C srtc/srtc_seconds/srtc_ripplecnt/COUNTER_LP.srtc_ripplereg/RIPPLE_REG[0].dataout[0]/C srtc/srtc_seconds/srtc_ripplecnt/COUNTER_LP.srtc_ripplereg/RIPPLE_REG[0].dataout_125/C}] -period {1000.0}  -waveform {0 500.0} 

create_clock -name {ident_coreinst.comm_block_INST.tck}        [ get_pins {ident_coreinst_comm_block_INST/jtagi_clkbuf/O}]          -period {40}  -waveform {0 20.0}
create_clock -name {ident_coreinst.comm_block_INST.dr2_tck}    [ get_pins {ident_coreinst_comm_block_INST/jtagi_clkbuf2/O}]         -period {40}  -waveform {0 20.0}
create_clock -name {ident_coreinst.comm_block_INST.ch_update}  [ get_pins {ident_coreinst_comm_block_INST/jtagi_jtag_prim1/UPDATE}] -period {40}  -waveform {0 20.0}
create_clock -name {ident_coreinst.comm_block_INST.hcr_update} [ get_pins {ident_coreinst_comm_block_INST/jtagi_jtag_prim2/UPDATE}] -period {40}  -waveform {0 20.0}
create_clock -name {lsim_debug|fclk_div2_derived_clock}        [ get_nets lsim/lsim_debug/fclk_div2]                                -period {40}  -waveform {0 20.0}

create_generated_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}] -source [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/C}] -master_clock {osc_clk} -add -multiply_by 1

create_generated_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}] -source [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/C}] -master_clock {pll_ir} -add -multiply_by 1

create_clock -name {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0} [get_pins {lptimer/lptimer_prescaler/timer_prescale_out/Q}]  -period {  80.000} -waveform {0.000 40.000}

create_generated_clock -name {rgpio2p_12s_5s_160s_31_0s_0s_1s_248_Z33|ipp_do_gpio_1_derived_clock[2]} [get_pins {rpp_dual_cm0p_l5k/rpp_dual_cm0p_plat/rgpio2p/ipp_do_gpio_1[2]/Q}] -source [get_pins {rpp_dual_cm0p_l5k/rpp_dual_cm0p_plat/rgpio2p/ipp_do_gpio_1[2]/C}] -multiply_by 1

create_generated_clock -name {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock} [ get_pins {iic1/iic_cpu_regs/state_ff_ret_3/Q}]       -source [ get_pins {iic1/iic_cpu_regs/state_ff_ret_3/C}] -multiply_by 1
create_generated_clock -name {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}    [ get_pins {lsim/lsim_test_entry/q_tstcfg_lden_ret/Q}] -source [ get_pins {lsim/lsim_test_entry/q_tstcfg_lden_ret/C}] -multiply_by 1

################################
#     Set Clock Groups
################################
set_clock_groups -asynchronous -name {REAL} -group [get_clocks {real_clock}]


set_clock_groups -asynchronous -name {OSC}  -group [get_clocks {osc_clk lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock ref_clk}]


set_clock_groups -asynchronous -name {IRC}  -group [get_clocks {pll_ir lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1}]


set_clock_groups -asynchronous -name {SYS} -group  [get_clocks {pll_clkfb pll_flash pll_sample pll_sys lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock rgpio2p_12s_5s_160s_31_0s_0s_1s_248_Z33|ipp_do_gpio_1_derived_clock[2] lsim_debug|fclk_div2_derived_clock pll_bus lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}]

set_clock_groups -asynchronous -name {identify_jtag_group1} -group  [get_clocks {ident_coreinst.comm_block_INST.tck ident_coreinst.comm_block_INST.dr2_tck ident_coreinst.comm_block_INST.ch_update ident_coreinst.comm_block_INST.hcr_update}]


################################
#     Set Multicycle path
################################
set_false_path -rise_from  [get_clocks {ident_coreinst.comm_block_INST.ch_update}]
set_multicycle_path -setup -end -from  [get_clocks {lsim_debug|fclk_div2_derived_clock}]                            -to [get_clocks {lsim_debug|fclk_div2_derived_clock}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {lsim_debug|fclk_div2_derived_clock}]                            -to [get_clocks {lsim_debug|fclk_div2_derived_clock}] {1}
set_multicycle_path -setup -end -from  [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] -to [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] -to [get_clocks {lptimer_prescaler_4s_16s|timer_prescale_out_derived_clock_1_0}] {1}
set_multicycle_path -setup -end -from  [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}]      -to [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}]      -to [get_clocks {iic_cpu_regs_iic_cpu_regs_0|state_ff_ret_3_derived_clock}] {1}
set_multicycle_path -setup -end -from  [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}]         -to [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}] {2}
set_multicycle_path -hold  -end -from  [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}]         -to [get_clocks {lsim_test_entry_31_6_0|me_tstcfg_lden_c_derived_clock}] {1}

 

Now lets focus our attention on the clock generation portion of the constraints file.

 

When vivado is trying to set the clock groups it will throw an error and say it cant find the clock that is in the get clocks command. So a workaround this is to redefine the clock after running the particular set_clocks_group command and then re run the set_clocks_group command.

 

Is this just a tool problem. It seems pecular to me that the tool can find the created_clock after first running the set_clock_groups command then redefining the clock but it cant however set the clock group with a create_generated_clock instantiated clock because it cant find it.

 

Does anyone have any insight to this? I would like to be able to fix this problem without having to modify the constraints file everytime there is an update to the design if possible.

 

Best

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3 Replies
bwade
Scholar
Scholar
8,968 Views
Registered: ‎07-01-2008

Since this issue has to do with timing constraints, I suggest that you take this to the Timing Analysys forum.

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graces
Moderator
Moderator
8,958 Views
Registered: ‎07-16-2008

It sounds either the generated clocks in question are not created, or the names don't match.

 

To verify, you can open synthesized design in Vivado and run "report_clocks" command in Tcl Console. It will report all clocks in the design.

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siktap
Scholar
Scholar
8,951 Views
Registered: ‎06-14-2012

Moving to Timing

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