10-06-2020 06:59 PM
10-06-2020 08:39 PM
In your screenshot, WHS is a negative number, -0.737. This indicates your design is failing hold timing - but the color (blue) of the number is wrong and should be red.
Please tell us the version of Vivado you are using.
Hopefully someone from Xilinx will file a request to get this fixed.
10-06-2020 08:44 PM
I am using Vivado 2019.2. Also, it seems like DDR4 example synthesized design timing is failing on Vivado 2019.2. Can you verify that too?