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sasindugeemal
Observer
Observer
611 Views
Registered: ‎12-26-2019

Total hold slack fails while worst hold slack passing

I setup the Example design of DDR4 IP for  XCKU060-1FFVA1517C device. After synthesis it shows THS is failed. But the WHS is a positive value. Can you explain the reason behind it?

Thanks,

Sasindu

tim.PNG
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4 Replies
591 Views
Registered: ‎01-22-2015

@sasindugeemal 

In your screenshot, WHS is a negative number, -0.737.  This indicates your design is failing hold timing - but the color (blue) of the number is wrong and should be red.

Please tell us the version of Vivado you are using.  

Hopefully someone from Xilinx will file a request to get this fixed.

Mark

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sasindugeemal
Observer
Observer
584 Views
Registered: ‎12-26-2019

I am using Vivado 2019.2. Also, it seems like DDR4 example synthesized design timing is failing on Vivado 2019.2. Can you verify that too?

Thanks,

Sasindu

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avrumw
Expert
Expert
566 Views
Registered: ‎01-23-2009

Can you post the detailed timing report of the worst failing hold check?

Avrum

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sasindugeemal
Observer
Observer
560 Views
Registered: ‎12-26-2019

I have attached all the screenshots and .rpx file below

4.PNG
3.PNG
ddr_config.PNG
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