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Total read latency

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Visitor
Posts: 5
Registered: ‎02-26-2018

Total read latency

I am generating a BRAM single port ROM

It says it has a total read latency of two clocks

I am trying to figure out exactly what that means.

Does it mean this?

// Simple single port BRAM with two clocks of latency
// This model is for simulation only, not for synthesis
module single_port_bram_rom_sim(clk, address_read,data_from_memory);
	
	parameter address_length  = 11;
	
	input wire clk;
	input wire [address_length-1:0] address_read;
	output reg [7:0] data_from_memory;
	
	reg [7:0] bram [2**address_length-1:0];
	reg [7:0] latency_1, latency_2;
	
	
	always @(posedge clk) begin
			latency_1 <= bram[address_read];
	end

	always @(posedge clk) begin
			latency_2 <= latency_1;
	end
	
	always @(posedge clk) begin
			data_from_memory <= latency_2;
	end
	
endmodule

or does it mean the with only one latency register, and then to output?

Scholar
Posts: 410
Registered: ‎01-22-2015

Re: Total read latency

[ Edited ]

Hi David,

 

When the Block Memory Generator (8.4) IP is configured with “Primitives Output Register” checked(enabled), then this IP will report a BRAM read-latency of 2.  The timing diagram for this BRAM configuration is shown by the figure below which is from Xilinx document PG058.

BRAM_read_latency_2.jpg

As you can see from the figure:

   CLKA edge-1: ADDRA is sent to BRAM

   CLKA edge-2: output, REG1, of the BRAM changes (ON or slightly after this CLKA edge)

   CLKA edge-3: data is safely read from BRAM output, REG1

 

You can verify the Figure 3-22 timing diagram using Vivado simulation.

 

Cheers,

Mark